diff options
| author | Pan Nengyuan <pannengyuan@huawei.com> | 2019-12-10 15:14:37 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2020-01-16 10:02:40 -0800 |
| commit | bb8136df698bd565ee4f6c18d26c50dee320bfe4 (patch) | |
| tree | 201f30a65e0a0a3366a699a1b18028ade66fdea5 /hw/riscv | |
| parent | 28b58f19d269633b3d14b6aebf1e92b3cd3ab56e (diff) | |
| download | qemu-bb8136df698bd565ee4f6c18d26c50dee320bfe4.zip | |
riscv/sifive_u: fix a memory leak in soc_realize()
Fix a minor memory leak in riscv_sifive_u_soc_realize()
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/sifive_u.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 0140e95732..0e12b3ccef 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -542,6 +542,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) SIFIVE_U_PLIC_CONTEXT_BASE, SIFIVE_U_PLIC_CONTEXT_STRIDE, memmap[SIFIVE_U_PLIC].size); + g_free(plic_hart_config); sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, |