diff options
| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2014-02-25 16:38:54 -0800 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2014-02-26 14:54:45 +1000 |
| commit | 81cce07ec6217351d291fc318fb8bf2d8f865032 (patch) | |
| tree | c0410373458baa78d7b06a17ae1c13d3ec92ac78 /hw/ppc | |
| parent | 05a738c4eca9e809226dec4b83624a3bad8066ee (diff) | |
| download | qemu-81cce07ec6217351d291fc318fb8bf2d8f865032.zip | |
ppc/virtex_ml507: Define macros for irq/memory maps
Define macros for the interrupt and memory maps for the sake of self
documentation.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Diffstat (limited to 'hw/ppc')
| -rw-r--r-- | hw/ppc/virtex_ml507.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index bdb057e36c..88312f88d9 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -45,6 +45,14 @@ #define EPAPR_MAGIC (0x45504150) #define FLASH_SIZE (16 * 1024 * 1024) +#define INTC_BASEADDR 0x81800000 +#define UART16550_BASEADDR 0x83e01003 +#define TIMER_BASEADDR 0x83c00000 +#define PFLASH_BASEADDR 0xfc000000 + +#define TIMER_IRQ 3 +#define UART16550_IRQ 9 + static struct boot_info { uint32_t bootstrap_pc; @@ -204,7 +212,7 @@ static void virtex_init(QEMUMachineInitArgs *args) memory_region_add_subregion(address_space_mem, ram_base, phys_ram); dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(0xfc000000, NULL, "virtex.flash", FLASH_SIZE, + pflash_cfi01_register(PFLASH_BASEADDR, NULL, "virtex.flash", FLASH_SIZE, dinfo ? dinfo->bdrv : NULL, (64 * 1024), FLASH_SIZE >> 16, 1, 0x89, 0x18, 0x0000, 0x0, 1); @@ -215,8 +223,8 @@ static void virtex_init(QEMUMachineInitArgs *args) irq[i] = qdev_get_gpio_in(dev, i); } - serial_mm_init(address_space_mem, 0x83e01003ULL, 2, irq[9], 115200, - serial_hds[0], DEVICE_LITTLE_ENDIAN); + serial_mm_init(address_space_mem, UART16550_BASEADDR, 2, irq[UART16550_IRQ], + 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN); /* 2 timers at irq 2 @ 62 Mhz. */ xilinx_timer_create(0x83c00000, irq[3], 0, 62 * 1000000); |