diff options
author | Alexander Wagner <alexander.wagner@ulal.de> | 2021-03-09 16:21:30 +0100 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2021-03-22 21:54:40 -0400 |
commit | 82a4ed8e5014ee814c63be33987e6783d5eacce2 (patch) | |
tree | cf3d201721301c39b3442d2eb73e95fb7c2121ab /hw/char | |
parent | 5e437d3ccdccfd85f6e69ca60f921be2dab62c3c (diff) | |
download | qemu-82a4ed8e5014ee814c63be33987e6783d5eacce2.zip |
hw/char: disable ibex uart receive if the buffer is full
Not disabling the UART leads to QEMU overwriting the UART receive buffer with
the newest received byte. The rx_level variable is added to allow the use of
the existing OpenTitan driver libraries.
Signed-off-by: Alexander Wagner <alexander.wagner@ulal.de>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210309152130.13038-1-alexander.wagner@ulal.de
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/char')
-rw-r--r-- | hw/char/ibex_uart.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index edcaa30ade..73b8f2e45b 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -66,7 +66,8 @@ static int ibex_uart_can_receive(void *opaque) { IbexUartState *s = opaque; - if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) { + if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) + && !(s->uart_status & R_STATUS_RXFULL_MASK)) { return 1; } @@ -83,6 +84,11 @@ static void ibex_uart_receive(void *opaque, const uint8_t *buf, int size) s->uart_status &= ~R_STATUS_RXIDLE_MASK; s->uart_status &= ~R_STATUS_RXEMPTY_MASK; + /* The RXFULL is set after receiving a single byte + * as the FIFO buffers are not yet implemented. + */ + s->uart_status |= R_STATUS_RXFULL_MASK; + s->rx_level += 1; if (size > rx_fifo_level) { s->uart_intr_state |= R_INTR_STATE_RX_WATERMARK_MASK; @@ -199,6 +205,7 @@ static void ibex_uart_reset(DeviceState *dev) s->uart_timeout_ctrl = 0x00000000; s->tx_level = 0; + s->rx_level = 0; s->char_tx_time = (NANOSECONDS_PER_SECOND / 230400) * 10; @@ -243,11 +250,15 @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr, case R_RDATA: retvalue = s->uart_rdata; - if (s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) { + if ((s->uart_ctrl & R_CTRL_RX_ENABLE_MASK) && (s->rx_level > 0)) { qemu_chr_fe_accept_input(&s->chr); - s->uart_status |= R_STATUS_RXIDLE_MASK; - s->uart_status |= R_STATUS_RXEMPTY_MASK; + s->rx_level -= 1; + s->uart_status &= ~R_STATUS_RXFULL_MASK; + if (s->rx_level == 0) { + s->uart_status |= R_STATUS_RXIDLE_MASK; + s->uart_status |= R_STATUS_RXEMPTY_MASK; + } } break; case R_WDATA: @@ -261,7 +272,8 @@ static uint64_t ibex_uart_read(void *opaque, hwaddr addr, case R_FIFO_STATUS: retvalue = s->uart_fifo_status; - retvalue |= s->tx_level & 0x1F; + retvalue |= (s->rx_level & 0x1F) << R_FIFO_STATUS_RXLVL_SHIFT; + retvalue |= (s->tx_level & 0x1F) << R_FIFO_STATUS_TXLVL_SHIFT; qemu_log_mask(LOG_UNIMP, "%s: RX fifos are not supported\n", __func__); @@ -364,6 +376,7 @@ static void ibex_uart_write(void *opaque, hwaddr addr, s->uart_fifo_ctrl = value; if (value & R_FIFO_CTRL_RXRST_MASK) { + s->rx_level = 0; qemu_log_mask(LOG_UNIMP, "%s: RX fifos are not supported\n", __func__); } |