diff options
| author | Padmakar Kalghatgi <p.kalghatgi@samsung.com> | 2020-12-18 00:32:16 +0100 |
|---|---|---|
| committer | Klaus Jensen <k.jensen@samsung.com> | 2021-02-08 21:15:54 +0100 |
| commit | f4319477b4fd692b568c22ed97dde7f542a48ac9 (patch) | |
| tree | 446704014d45409e65ca22d2a287f5ac398fc308 /hw/block/trace-events | |
| parent | 7ec9f2eef979e51891d99667e01d6c0e789a52b2 (diff) | |
| download | qemu-f4319477b4fd692b568c22ed97dde7f542a48ac9.zip | |
hw/block/nvme: move cmb logic to v1.4
Implement v1.4 logic for configuring the Controller Memory Buffer. By
default, the v1.4 scheme will be used (CMB must be explicitly enabled by
the host), so drivers that only support v1.3 will not be able to use the
CMB anymore.
To retain the v1.3 behavior, set the boolean 'legacy-cmb' nvme device
parameter.
Reviewed-by: Keith Busch <kbusch@kernel.org>
Reviewed-by: Minwoo Im <minwoo.im.dev@gmail.com>
Signed-off-by: Padmakar Kalghatgi <p.kalghatgi@samsung.com>
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Diffstat (limited to 'hw/block/trace-events')
| -rw-r--r-- | hw/block/trace-events | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/block/trace-events b/hw/block/trace-events index 3772502033..87ab6c5090 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -123,6 +123,8 @@ pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8"" pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit) "Invalid LBA start=%"PRIu64" len=%"PRIu64" limit=%"PRIu64"" pci_nvme_err_invalid_log_page_offset(uint64_t ofs, uint64_t size) "must be <= %"PRIu64", got %"PRIu64"" +pci_nvme_err_cmb_invalid_cba(uint64_t cmbmsc) "cmbmsc 0x%"PRIx64"" +pci_nvme_err_cmb_not_enabled(uint64_t cmbmsc) "cmbmsc 0x%"PRIx64"" pci_nvme_err_unaligned_zone_cmd(uint8_t action, uint64_t slba, uint64_t zslba) "unaligned zone op 0x%"PRIx32", got slba=%"PRIu64", zslba=%"PRIu64"" pci_nvme_err_invalid_zone_state_transition(uint8_t action, uint64_t slba, uint8_t attrs) "action=0x%"PRIx8", slba=%"PRIu64", attrs=0x%"PRIx32"" pci_nvme_err_write_not_at_wp(uint64_t slba, uint64_t zone, uint64_t wp) "writing at slba=%"PRIu64", zone=%"PRIu64", but wp=%"PRIu64"" |