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authorSergey Sorokin <afarallax@yandex.ru>2016-06-06 16:59:32 +0100
committerPeter Maydell <peter.maydell@linaro.org>2016-06-06 16:59:32 +0100
commit6e99f762612827afeff54add2e4fc2c3b2657fed (patch)
treeeebb9f263135e16590b3413755071d3494c78801 /hw/arm/xlnx-ep108.c
parente5fabad7ccfd3b23afd370dba81a93cc280be60e (diff)
downloadqemu-6e99f762612827afeff54add2e4fc2c3b2657fed.zip
target-arm: Fix TTBR selecting logic on AArch32 Stage 2 translation
Address size is 40-bit for the AArch32 stage 2 translation, and t0sz can be negative (from -8 to 7), so we need to adjust it to use the existing TTBR selecting logic. Signed-off-by: Sergey Sorokin <afarallax@yandex.ru> Message-id: 1464974151-1231644-1-git-send-email-afarallax@yandex.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/arm/xlnx-ep108.c')
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