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authorRichard Henderson <richard.henderson@linaro.org>2021-03-23 12:43:31 -0600
committerDavid Gibson <david@gibson.dropbear.id.au>2021-05-04 11:41:24 +1000
commitedece45d4ac2a12a7183d8fb1ddd7f7984910ab8 (patch)
tree7e64af3ebda2e542a3243adf778e6e304ff4a438
parente81f17a3f616a4f2c803aafed60500ac45df9b3d (diff)
downloadqemu-edece45d4ac2a12a7183d8fb1ddd7f7984910ab8.zip
target/ppc: Extract post_load_update_msr
Extract post_load_update_msr to share between cpu_load_old and cpu_post_load in updating the msr. Suggested-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210323184340.619757-2-richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
-rw-r--r--target/ppc/machine.c30
1 files changed, 14 insertions, 16 deletions
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 1f7a353c78..09c5765a87 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -10,6 +10,18 @@
#include "kvm_ppc.h"
#include "exec/helper-proto.h"
+static void post_load_update_msr(CPUPPCState *env)
+{
+ target_ulong msr = env->msr;
+
+ /*
+ * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
+ * before restoring. Note that this recomputes hflags and mem_idx.
+ */
+ env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
+ ppc_store_msr(env, msr);
+}
+
static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
{
PowerPCCPU *cpu = opaque;
@@ -21,7 +33,6 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
int32_t slb_nr;
#endif
target_ulong xer;
- target_ulong msr;
for (i = 0; i < 32; i++) {
qemu_get_betls(f, &env->gpr[i]);
@@ -117,13 +128,7 @@ static int cpu_load_old(QEMUFile *f, void *opaque, int version_id)
qemu_get_sbe32(f); /* Discard unused mmu_idx */
qemu_get_sbe32(f); /* Discard unused power_mode */
- /*
- * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
- * before restoring. Note that this recomputes hflags and mem_idx.
- */
- msr = env->msr;
- env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
- ppc_store_msr(env, msr);
+ post_load_update_msr(env);
return 0;
}
@@ -343,7 +348,6 @@ static int cpu_post_load(void *opaque, int version_id)
PowerPCCPU *cpu = opaque;
CPUPPCState *env = &cpu->env;
int i;
- target_ulong msr;
/*
* If we're operating in compat mode, we should be ok as long as
@@ -417,13 +421,7 @@ static int cpu_post_load(void *opaque, int version_id)
ppc_store_sdr1(env, env->spr[SPR_SDR1]);
}
- /*
- * Invalidate all supported msr bits except MSR_TGPR/MSR_HVB
- * before restoring. Note that this recomputes hflags and mem_idx.
- */
- msr = env->msr;
- env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
- ppc_store_msr(env, msr);
+ post_load_update_msr(env);
return 0;
}