diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-10-15 17:00:18 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-10-15 17:00:18 +0000 |
| commit | f0aabd1aa335cecc01eddf16369c4be625df4d13 (patch) | |
| tree | f9dc934cf0035ee473631b188e9e2d863badd456 | |
| parent | e2be8d8d7ed7ca8bd3fdf7f6207cabd9cfb32b8e (diff) | |
| download | qemu-f0aabd1aa335cecc01eddf16369c4be625df4d13.zip | |
PPC: convert SPE effective address computation to TCG
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5491 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-ppc/translate.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 997514467e..76cedac6d5 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -5316,17 +5316,16 @@ static always_inline void gen_speundef (DisasContext *ctx) } /* SPE load and stores */ -static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh) +static always_inline void gen_addr_spe_imm_index (TCGv EA, DisasContext *ctx, int sh) { target_long simm = rB(ctx->opcode); - if (rA(ctx->opcode) == 0) { - tcg_gen_movi_tl(cpu_T[0], simm << sh); - } else { - tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]); - if (likely(simm != 0)) - tcg_gen_addi_tl(cpu_T[0], cpu_T[0], simm << sh); - } + if (rA(ctx->opcode) == 0) + tcg_gen_movi_tl(EA, simm << sh); + else if (likely(simm != 0)) + tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm << sh); + else + tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); } #define op_spe_ldst(name) (*gen_op_##name[ctx->mem_idx])() @@ -5346,7 +5345,7 @@ static always_inline void gen_evl##name (DisasContext *ctx) \ GEN_EXCP_NO_AP(ctx); \ return; \ } \ - gen_addr_spe_imm_index(ctx, sh); \ + gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \ op_spe_ldst(spe_l##name); \ gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]); \ } @@ -5375,7 +5374,7 @@ static always_inline void gen_evst##name (DisasContext *ctx) \ GEN_EXCP_NO_AP(ctx); \ return; \ } \ - gen_addr_spe_imm_index(ctx, sh); \ + gen_addr_spe_imm_index(cpu_T[0], ctx, sh); \ gen_load_gpr64(cpu_T64[1], rS(ctx->opcode)); \ op_spe_ldst(spe_st##name); \ } |