diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:35:58 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-04-29 17:35:58 +0100 |
| commit | ef9aae2522c22c05df17dd898099dd5c3f20d688 (patch) | |
| tree | b4a68ca0b1010286f9644c4991e5c91e074f08ae | |
| parent | d33abe82c7c9847284a23e575e1078cccab540b5 (diff) | |
| download | qemu-ef9aae2522c22c05df17dd898099dd5c3f20d688.zip | |
target/arm: Disable most VFP sysregs for M-profile
The only "system register" that M-profile floating point exposes
via the VMRS/VMRS instructions is FPSCR, and it does not have
the odd special case for rd==15. Add a check to ensure we only
expose FPSCR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190416125744.27770-5-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/translate.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 4ea4018e2b..a978453506 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3513,12 +3513,27 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) } } } else { /* !dp */ + bool is_sysreg; + if ((insn & 0x6f) != 0x00) return 1; rn = VFP_SREG_N(insn); + + is_sysreg = extract32(insn, 21, 1); + + if (arm_dc_feature(s, ARM_FEATURE_M)) { + /* + * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. + * Writes to R15 are UNPREDICTABLE; we choose to undef. + */ + if (is_sysreg && (rd == 15 || (rn >> 1) != ARM_VFP_FPSCR)) { + return 1; + } + } + if (insn & ARM_CP_RW_BIT) { /* vfp->arm */ - if (insn & (1 << 21)) { + if (is_sysreg) { /* system register */ rn >>= 1; @@ -3585,7 +3600,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) } } else { /* arm->vfp */ - if (insn & (1 << 21)) { + if (is_sysreg) { rn >>= 1; /* system register */ switch (rn) { |