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| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-07 22:33:22 +0100 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-12-13 19:58:54 +0100 |
| commit | df6adb68c1b1808f164c9ed8a04fe14d9c04e82c (patch) | |
| tree | 9ca6f70276d7e91c3f96e60d7e114e103ab41348 | |
| parent | ac70f9767cba3a5966f7eefc102fcda8b3c7d09e (diff) | |
| download | qemu-df6adb68c1b1808f164c9ed8a04fe14d9c04e82c.zip | |
target/mips: Introduce cpu_supports_isa() taking CPUMIPSState argument
Introduce cpu_supports_isa() which takes a CPUMIPSState
argument, more useful at runtime when the CPU is created
(no need to call the extensive object_class_by_name()).
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201207215257.4004222-3-f4bug@amsat.org>
| -rw-r--r-- | target/mips/cpu.c | 5 | ||||
| -rw-r--r-- | target/mips/cpu.h | 1 |
2 files changed, 6 insertions, 0 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 76d50b00b4..687e2680dd 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -310,3 +310,8 @@ MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk) return MIPS_CPU(cpu); } + +bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) +{ + return (env->cpu_model->insn_flags & isa_mask) != 0; +} diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 9c65c87bf9..e8bca75f23 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1287,6 +1287,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU bool cpu_type_supports_cps_smp(const char *cpu_type); +bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask); bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa); void cpu_set_exception_base(int vp_index, target_ulong address); |