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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-01-27 15:20:25 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-01-27 15:29:08 +0000 |
| commit | d87576e38df760ef1cb635197d51f207e2a8eda9 (patch) | |
| tree | d0cb56d4a824b42706ae2056cdf71be6539dd749 | |
| parent | e62694a078f182c822a7b6d3976b1bcc72e78ec2 (diff) | |
| download | qemu-d87576e38df760ef1cb635197d51f207e2a8eda9.zip | |
arm_gicv3: Fix broken logic in ELRSR calculation
Fix a broken expression in the calculation of ELRSR
register bits: instead of "(lr & ICH_LR_EL2_HW) == 1"
we want to check for != 0, because the HW bit is not
bit 0 so a test for == 1 is always false.
Fixes: https://bugs.launchpad.net/bugs/1658506
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 1485255993-6322-1-git-send-email-peter.maydell@linaro.org
| -rw-r--r-- | hw/intc/arm_gicv3_cpuif.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index a9ee7fddf9..c25ee03556 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2430,7 +2430,7 @@ static uint64_t ich_elrsr_read(CPUARMState *env, const ARMCPRegInfo *ri) uint64_t lr = cs->ich_lr_el2[i]; if ((lr & ICH_LR_EL2_STATE_MASK) == 0 && - ((lr & ICH_LR_EL2_HW) == 1 || (lr & ICH_LR_EL2_EOI) == 0)) { + ((lr & ICH_LR_EL2_HW) != 0 || (lr & ICH_LR_EL2_EOI) == 0)) { value |= (1 << i); } } |