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| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2014-06-04 22:50:55 +1000 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:44 +0200 |
| commit | d1a721ab816d1b954c0988aafdec4e109b953a9f (patch) | |
| tree | dcb64980cc93a87f9b3319f1321f79b7302b9b5f | |
| parent | a242881405811ec6e6134452311f1cd1896c8ada (diff) | |
| download | qemu-d1a721ab816d1b954c0988aafdec4e109b953a9f.zip | |
target-ppc: Add POWER8's TIR SPR
This adds TIR (Thread Identification Register) SPR first defined for server
CPUs in PowerISA 2.07.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target-ppc/cpu.h | 1 | ||||
| -rw-r--r-- | target-ppc/translate_init.c | 10 |
2 files changed, 11 insertions, 0 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 6a53d70af5..9f9ffb174d 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1370,6 +1370,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) #define SPR_BOOKE_GIVOR8 (0x1BB) #define SPR_BOOKE_GIVOR13 (0x1BC) #define SPR_BOOKE_GIVOR14 (0x1BD) +#define SPR_TIR (0x1BE) #define SPR_BOOKE_SPEFSCR (0x200) #define SPR_Exxx_BBEAR (0x201) #define SPR_Exxx_BBTAR (0x202) diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 7eb02acaba..1df69e0cfd 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7518,6 +7518,15 @@ static void gen_spr_book3s_ids(CPUPPCState *env) 0x00000000); } +static void gen_spr_power8_ids(CPUPPCState *env) +{ + /* Thread identification */ + spr_register(env, SPR_TIR, "TIR", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, SPR_NOACCESS, + 0x00000000); +} + static void gen_spr_book3s_purr(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) @@ -7621,6 +7630,7 @@ static void init_proc_book3s_64(CPUPPCState *env, int version) } if (version >= BOOK3S_CPU_POWER8) { gen_spr_power8_tce_address_control(env); + gen_spr_power8_ids(env); } #if !defined(CONFIG_USER_ONLY) switch (version) { |