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| author | Thomas Hanson <thomas.hanson@linaro.org> | 2016-10-17 19:22:18 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-10-17 19:22:18 +0100 |
| commit | 957956b3013c8122a749dfe61a41aef8b4100e31 (patch) | |
| tree | 5d4e1b61a78cc5085a7e3d391e8d1f942e51569c | |
| parent | 6feecb8b941f2d21e5645d0b6e0cdb776998121b (diff) | |
| download | qemu-957956b3013c8122a749dfe61a41aef8b4100e31.zip | |
target-arm: Comments added to identify cases in a switch
3 cases in a switch in disas_exc() require reference to the
ARM ARM spec in order to determine what case they're handling.
Signed-off-by: Thomas Hanson <thomas.hanson@linaro.org>
Message-id: 1476301853-15774-5-git-send-email-thomas.hanson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-arm/translate-a64.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 16716a2c1f..96c222722e 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1667,12 +1667,12 @@ static void disas_exc(DisasContext *s, uint32_t insn) * instruction works properly. */ switch (op2_ll) { - case 1: + case 1: /* SVC */ gen_ss_advance(s); gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16), default_exception_el(s)); break; - case 2: + case 2: /* HVC */ if (s->current_el == 0) { unallocated_encoding(s); break; @@ -1685,7 +1685,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) gen_ss_advance(s); gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2); break; - case 3: + case 3: /* SMC */ if (s->current_el == 0) { unallocated_encoding(s); break; |