diff options
| author | Yongbok Kim <yongbok.kim@mips.com> | 2018-08-02 16:16:15 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-08-24 17:51:59 +0200 |
| commit | 7ef009b2dd72852505c7348c0bd1f8eb1e62a064 (patch) | |
| tree | 91e03082a4b73b9fcd31769d09ac61f1f74e8ceb | |
| parent | 4d18232ca0f903df099d243ccfe28b0e545dc92d (diff) | |
| download | qemu-7ef009b2dd72852505c7348c0bd1f8eb1e62a064.zip | |
target/mips: Add emulation of nanoMIPS 48-bit instructions
Add emulation of LI48, ADDIU48, ADDIUGP48, ADDIUPC48, LWPC48, and
SWPC48 instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
| -rw-r--r-- | target/mips/translate.c | 66 |
1 files changed, 65 insertions, 1 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 8bc08f742e..98df88ee4d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16946,7 +16946,71 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_P48I: - return 6; + { + insn = cpu_lduw_code(env, ctx->base.pc_next + 4); + target_long addr_off = extract32(ctx->opcode, 0, 16) | insn << 16; + switch (extract32(ctx->opcode, 16, 5)) { + case NM_LI48: + if (rt != 0) { + tcg_gen_movi_tl(cpu_gpr[rt], addr_off); + } + break; + case NM_ADDIU48: + if (rt != 0) { + tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rt], addr_off); + tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); + } + break; + case NM_ADDIUGP48: + if (rt != 0) { + gen_op_addr_addi(ctx, cpu_gpr[rt], cpu_gpr[28], addr_off); + } + break; + case NM_ADDIUPC48: + if (rt != 0) { + target_long addr = addr_add(ctx, ctx->base.pc_next + 6, + addr_off); + + tcg_gen_movi_tl(cpu_gpr[rt], addr); + } + break; + case NM_LWPC48: + if (rt != 0) { + TCGv t0; + t0 = tcg_temp_new(); + + target_long addr = addr_add(ctx, ctx->base.pc_next + 6, + addr_off); + + tcg_gen_movi_tl(t0, addr); + tcg_gen_qemu_ld_tl(cpu_gpr[rt], t0, ctx->mem_idx, MO_TESL); + tcg_temp_free(t0); + } + break; + case NM_SWPC48: + { + TCGv t0, t1; + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + target_long addr = addr_add(ctx, ctx->base.pc_next + 6, + addr_off); + + tcg_gen_movi_tl(t0, addr); + gen_load_gpr(t1, rt); + + tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); + + tcg_temp_free(t0); + tcg_temp_free(t1); + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + return 6; + } case NM_P_U12: switch (extract32(ctx->opcode, 12, 4)) { case NM_ORI: |