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| author | Maciej W. Rozycki <macro@codesourcery.com> | 2014-11-04 15:38:05 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-07 14:15:28 +0000 |
| commit | 70409e6726aa6ece565c8732f6c5cb5cd5879716 (patch) | |
| tree | 0d0ce65392c5e1bdbc6e2311553eec7ef0f49808 | |
| parent | 272f458dc8d860f30add3b6a3fff9ad9876aadc1 (diff) | |
| download | qemu-70409e6726aa6ece565c8732f6c5cb5cd5879716.zip | |
mips: Add macros for CP0.Config3 and CP0.Config4 bits
Define macros for CP0.Config3 and CP0.Config4 bits. These used to be
exhaustive as at MIPS32r3, but more bits may have been added since.
Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| -rw-r--r-- | target-mips/cpu.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index d21da8eb8c..c01bbdac2d 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -424,17 +424,25 @@ struct CPUMIPSState { #define CP0C2_SA 0 int32_t CP0_Config3; #define CP0C3_M 31 +#define CP0C3_BPG 30 +#define CP0C3_CMCGR 29 #define CP0C3_MSAP 28 #define CP0C3_BP 27 #define CP0C3_BI 26 +#define CP0C3_IPLW 21 +#define CP0C3_MMAR 18 +#define CP0C3_MCU 17 #define CP0C3_ISA_ON_EXC 16 +#define CP0C3_ISA 14 #define CP0C3_ULRI 13 #define CP0C3_RXI 12 +#define CP0C3_DSP2P 11 #define CP0C3_DSPP 10 #define CP0C3_LPA 7 #define CP0C3_VEIC 6 #define CP0C3_VInt 5 #define CP0C3_SP 4 +#define CP0C3_CDMM 3 #define CP0C3_MT 2 #define CP0C3_SM 1 #define CP0C3_TL 0 @@ -443,6 +451,11 @@ struct CPUMIPSState { #define CP0C4_M 31 #define CP0C4_IE 29 #define CP0C4_KScrExist 16 +#define CP0C4_MMUExtDef 14 +#define CP0C4_FTLBPageSize 8 +#define CP0C4_FTLBWays 4 +#define CP0C4_FTLBSets 0 +#define CP0C4_MMUSizeExt 0 uint32_t CP0_Config5; uint32_t CP0_Config5_rw_bitmask; #define CP0C5_M 31 |