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| author | Peter Maydell <peter.maydell@linaro.org> | 2017-10-09 14:48:35 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2017-10-12 13:23:14 +0100 |
| commit | 6b8acf256df09c8a8dd7dcaa79b06eaff4ad63f7 (patch) | |
| tree | b511012e041a0040c4c24c933e78f9a8c146ba54 | |
| parent | d02a8698d7ae2bfed3b11fe5b064cb0aa406863b (diff) | |
| download | qemu-6b8acf256df09c8a8dd7dcaa79b06eaff4ad63f7.zip | |
target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1
The code which implements the Thumb1 split BL/BLX instructions
is guarded by a check on "not M or THUMB2". All we really need
to check here is "not THUMB2" (and we assume that elsewhere too,
eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns).
This doesn't change behaviour because all M profile cores
have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2.
(v6M implements a very restricted subset of Thumb2, but we
can cross that bridge when we get to it with appropriate
feature bits.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1507556919-24992-6-git-send-email-peter.maydell@linaro.org
| -rw-r--r-- | target/arm/translate.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c index 5c6f9fea1b..530a5c4ac0 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9719,8 +9719,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw int conds; int logic_cc; - if (!(arm_dc_feature(s, ARM_FEATURE_THUMB2) - || arm_dc_feature(s, ARM_FEATURE_M))) { + if (!arm_dc_feature(s, ARM_FEATURE_THUMB2)) { /* Thumb-1 cores may need to treat bl and blx as a pair of 16-bit instructions to get correct prefetch abort behavior. */ insn = insn_hw1; |