diff options
| author | Tom Musta <tommusta@gmail.com> | 2014-01-15 08:10:33 -0600 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-03-05 03:06:34 +0100 |
| commit | 3fd0aadfc19ba146ed6ced27b4e6ff6afc08473a (patch) | |
| tree | a94707d2019eb699948c641601bc0fac5adc76c4 | |
| parent | e16a626b8280cfcf3de385c59ddd1fde2840c2c3 (diff) | |
| download | qemu-3fd0aadfc19ba146ed6ced27b4e6ff6afc08473a.zip | |
target-ppc: VSX Stage 4: Add xsaddsp and xssubsp
This patch adds the VSX Scalar Add Single-Precision (xsaddsp) and
VSX Scalar Subtract Single-Precision (xssubsp) instructions.
The existing VSX_ADD_SUB macro is modified to support the rounding
of the (intermediate) result to single-precision.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | target-ppc/fpu_helper.c | 20 | ||||
| -rw-r--r-- | target-ppc/helper.h | 3 | ||||
| -rw-r--r-- | target-ppc/translate.c | 6 |
3 files changed, 22 insertions, 7 deletions
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index 3165ef0ac4..f0476409aa 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1768,7 +1768,7 @@ static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) * fld - vsr_t field (f32 or f64) * sfprf - set FPRF */ -#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf) \ +#define VSX_ADD_SUB(name, op, nels, tp, fld, sfprf, r2sp) \ void helper_##name(CPUPPCState *env, uint32_t opcode) \ { \ ppc_vsr_t xt, xa, xb; \ @@ -1794,6 +1794,10 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ } \ } \ \ + if (r2sp) { \ + xt.fld[i] = helper_frsp(env, xt.fld[i]); \ + } \ + \ if (sfprf) { \ helper_compute_fprf(env, xt.fld[i], sfprf); \ } \ @@ -1802,12 +1806,14 @@ void helper_##name(CPUPPCState *env, uint32_t opcode) \ helper_float_check_status(env); \ } -VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1) -VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0) -VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0) -VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1) -VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0) -VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0) +VSX_ADD_SUB(xsadddp, add, 1, float64, f64, 1, 0) +VSX_ADD_SUB(xsaddsp, add, 1, float64, f64, 1, 1) +VSX_ADD_SUB(xvadddp, add, 2, float64, f64, 0, 0) +VSX_ADD_SUB(xvaddsp, add, 4, float32, f32, 0, 0) +VSX_ADD_SUB(xssubdp, sub, 1, float64, f64, 1, 0) +VSX_ADD_SUB(xssubsp, sub, 1, float64, f64, 1, 1) +VSX_ADD_SUB(xvsubdp, sub, 2, float64, f64, 0, 0) +VSX_ADD_SUB(xvsubsp, sub, 4, float32, f32, 0, 0) /* VSX_MUL - VSX floating point multiply * op - instruction mnemonic diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 0276b02511..696b9d35ac 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -286,6 +286,9 @@ DEF_HELPER_2(xsrdpim, void, env, i32) DEF_HELPER_2(xsrdpip, void, env, i32) DEF_HELPER_2(xsrdpiz, void, env, i32) +DEF_HELPER_2(xsaddsp, void, env, i32) +DEF_HELPER_2(xssubsp, void, env, i32) + DEF_HELPER_2(xvadddp, void, env, i32) DEF_HELPER_2(xvsubdp, void, env, i32) DEF_HELPER_2(xvmuldp, void, env, i32) diff --git a/target-ppc/translate.c b/target-ppc/translate.c index d67bf2d4fe..f0925d50a1 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -7358,6 +7358,9 @@ GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX) GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX) +GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207) +GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207) + GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX) GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX) @@ -10164,6 +10167,9 @@ GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX), GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX), GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX), +GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207), +GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207), + GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX), GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX), GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX), |