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authorHans-Erik Floryd <hans-erik.floryd@rt-labs.com>2018-08-20 11:24:31 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-08-20 11:24:31 +0100
commit3c54cf7705f243c0d37f254abd0131ab69ae94e5 (patch)
tree7b802eff843ca21a6353a87ed0ba755c6b2545ec
parent84be3ef1defeefc4ef157f8657d178d204ec0f3a (diff)
downloadqemu-3c54cf7705f243c0d37f254abd0131ab69ae94e5.zip
imx_serial: Generate interrupt on receive data ready if enabled
Generate an interrupt if USR2_RDR and UCR4_DREN are both set. Signed-off-by: Hans-Erik Floryd <hans-erik.floryd@rt-labs.com> Message-id: 1534341354-11956-1-git-send-email-hans-erik.floryd@rt-labs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--hw/char/imx_serial.c3
-rw-r--r--include/hw/char/imx_serial.h1
2 files changed, 3 insertions, 1 deletions
diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c
index 0747db9f2b..1e363190e3 100644
--- a/hw/char/imx_serial.c
+++ b/hw/char/imx_serial.c
@@ -74,8 +74,9 @@ static void imx_update(IMXSerialState *s)
mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
/*
* TCEN and TXDC are both bit 3
+ * RDR and DREN are both bit 0
*/
- mask |= s->ucr4 & UCR4_TCEN;
+ mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN);
usr2 = s->usr2 & mask;
diff --git a/include/hw/char/imx_serial.h b/include/hw/char/imx_serial.h
index ee80da12e6..c8b74284f8 100644
--- a/include/hw/char/imx_serial.h
+++ b/include/hw/char/imx_serial.h
@@ -68,6 +68,7 @@
#define UCR2_RXEN (1<<1) /* Receiver enable */
#define UCR2_SRST (1<<0) /* Reset complete */
+#define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */
#define UCR4_TCEN BIT(3) /* TX complete interrupt enable */
#define UTS1_TXEMPTY (1<<6)