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author | Peter Maydell <peter.maydell@linaro.org> | 2019-07-01 13:47:20 +0100 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2019-07-01 13:47:21 +0100 |
commit | 39d1b92b810793e02558e05efa23059f67520bc9 (patch) | |
tree | f57917d564b19c5a5a95ffbde1adcca4a43079f9 | |
parent | ab67678a59e31d30b0f8587cdc245f93c2e56fef (diff) | |
parent | 8317ea0607a2d01b3cb6329aef1b8c8ca00471e1 (diff) | |
download | qemu-39d1b92b810793e02558e05efa23059f67520bc9.zip |
Merge remote-tracking branch 'remotes/bkoppelmann2/tags/pull-tricore-20190625' into staging
* Add FTOIZ/UTOF/QSEED insns
* Fix sync of hflags and swapped args of RRPW_INSERT
# gpg: Signature made Tue 25 Jun 2019 14:05:03 BST
# gpg: using RSA key 6E636A7E83F2DD0CFA6E6E370AD2C6396B69CA14
# gpg: issuer "kbastian@mail.uni-paderborn.de"
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" [full]
# Primary key fingerprint: 6E63 6A7E 83F2 DD0C FA6E 6E37 0AD2 C639 6B69 CA14
* remotes/bkoppelmann2/tags/pull-tricore-20190625:
tricore: add QSEED instruction
tricore: sync ctx.hflags with tb->flags
tricore: fix RRPW_INSERT instruction
tricore: add UTOF instruction
tricore: add FTOIZ instruction
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | target/tricore/fpu_helper.c | 126 | ||||
-rw-r--r-- | target/tricore/helper.h | 3 | ||||
-rw-r--r-- | target/tricore/translate.c | 14 |
3 files changed, 141 insertions, 2 deletions
diff --git a/target/tricore/fpu_helper.c b/target/tricore/fpu_helper.c index d8a6c0d25b..cb7ee7dd35 100644 --- a/target/tricore/fpu_helper.c +++ b/target/tricore/fpu_helper.c @@ -24,6 +24,7 @@ #define QUIET_NAN 0x7fc00000 #define ADD_NAN 0x7fc00001 +#define SQRT_NAN 0x7fc00004 #define DIV_NAN 0x7fc00008 #define MUL_NAN 0x7fc00002 #define FPU_FS PSW_USB_C @@ -32,6 +33,9 @@ #define FPU_FZ PSW_USB_AV #define FPU_FU PSW_USB_SAV +#define float32_sqrt_nan make_float32(SQRT_NAN) +#define float32_quiet_nan make_float32(QUIET_NAN) + /* we don't care about input_denormal */ static inline uint8_t f_get_excp_flags(CPUTriCoreState *env) { @@ -166,6 +170,87 @@ uint32_t helper_fmul(CPUTriCoreState *env, uint32_t r1, uint32_t r2) } +/* + * Target TriCore QSEED.F significand Lookup Table + * + * The QSEED.F output significand depends on the least-significant + * exponent bit and the 6 most-significant significand bits. + * + * IEEE 754 float datatype + * partitioned into Sign (S), Exponent (E) and Significand (M): + * + * S E E E E E E E E M M M M M M ... + * | | | + * +------+------+-------+-------+ + * | | + * for lookup table + * calculating index for + * output E output M + * + * This lookup table was extracted by analyzing QSEED output + * from the real hardware + */ +static const uint8_t target_qseed_significand_table[128] = { + 253, 252, 245, 244, 239, 238, 231, 230, 225, 224, 217, 216, + 211, 210, 205, 204, 201, 200, 195, 194, 189, 188, 185, 184, + 179, 178, 175, 174, 169, 168, 165, 164, 161, 160, 157, 156, + 153, 152, 149, 148, 145, 144, 141, 140, 137, 136, 133, 132, + 131, 130, 127, 126, 123, 122, 121, 120, 117, 116, 115, 114, + 111, 110, 109, 108, 103, 102, 99, 98, 93, 92, 89, 88, 83, + 82, 79, 78, 75, 74, 71, 70, 67, 66, 63, 62, 59, 58, 55, + 54, 53, 52, 49, 48, 45, 44, 43, 42, 39, 38, 37, 36, 33, + 32, 31, 30, 27, 26, 25, 24, 23, 22, 19, 18, 17, 16, 15, + 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2 +}; + +uint32_t helper_qseed(CPUTriCoreState *env, uint32_t r1) +{ + uint32_t arg1, S, E, M, E_minus_one, m_idx; + uint32_t new_E, new_M, new_S, result; + + arg1 = make_float32(r1); + + /* fetch IEEE-754 fields S, E and the uppermost 6-bit of M */ + S = extract32(arg1, 31, 1); + E = extract32(arg1, 23, 8); + M = extract32(arg1, 17, 6); + + if (float32_is_any_nan(arg1)) { + result = float32_quiet_nan; + } else if (float32_is_zero_or_denormal(arg1)) { + if (float32_is_neg(arg1)) { + result = float32_infinity | (1 << 31); + } else { + result = float32_infinity; + } + } else if (float32_is_neg(arg1)) { + result = float32_sqrt_nan; + } else if (float32_is_infinity(arg1)) { + result = float32_zero; + } else { + E_minus_one = E - 1; + m_idx = ((E_minus_one & 1) << 6) | M; + new_S = S; + new_E = 0xBD - E_minus_one / 2; + new_M = target_qseed_significand_table[m_idx]; + + result = 0; + result = deposit32(result, 31, 1, new_S); + result = deposit32(result, 23, 8, new_E); + result = deposit32(result, 15, 8, new_M); + } + + if (float32_is_signaling_nan(arg1, &env->fp_status) + || result == float32_sqrt_nan) { + env->FPU_FI = 1 << 31; + env->FPU_FS = 1; + } else { + env->FPU_FS = 0; + } + + return (uint32_t) result; +} + uint32_t helper_fdiv(CPUTriCoreState *env, uint32_t r1, uint32_t r2) { uint32_t flags; @@ -303,6 +388,47 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg) return (uint32_t)f_result; } +uint32_t helper_utof(CPUTriCoreState *env, uint32_t arg) +{ + float32 f_result; + uint32_t flags; + + f_result = uint32_to_float32(arg, &env->fp_status); + + flags = f_get_excp_flags(env); + if (flags) { + f_update_psw_flags(env, flags); + } else { + env->FPU_FS = 0; + } + return (uint32_t)f_result; +} + +uint32_t helper_ftoiz(CPUTriCoreState *env, uint32_t arg) +{ + float32 f_arg = make_float32(arg); + uint32_t result; + int32_t flags; + + result = float32_to_int32_round_to_zero(f_arg, &env->fp_status); + + flags = f_get_excp_flags(env); + if (flags & float_flag_invalid) { + flags &= ~float_flag_inexact; + if (float32_is_any_nan(f_arg)) { + result = 0; + } + } + + if (flags) { + f_update_psw_flags(env, flags); + } else { + env->FPU_FS = 0; + } + + return result; +} + uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg) { float32 f_arg = make_float32(arg); diff --git a/target/tricore/helper.h b/target/tricore/helper.h index f60e81096b..b64780c37d 100644 --- a/target/tricore/helper.h +++ b/target/tricore/helper.h @@ -109,8 +109,11 @@ DEF_HELPER_3(fdiv, i32, env, i32, i32) DEF_HELPER_4(fmadd, i32, env, i32, i32, i32) DEF_HELPER_4(fmsub, i32, env, i32, i32, i32) DEF_HELPER_3(fcmp, i32, env, i32, i32) +DEF_HELPER_2(qseed, i32, env, i32) DEF_HELPER_2(ftoi, i32, env, i32) DEF_HELPER_2(itof, i32, env, i32) +DEF_HELPER_2(utof, i32, env, i32) +DEF_HELPER_2(ftoiz, i32, env, i32) DEF_HELPER_2(ftouz, i32, env, i32) DEF_HELPER_2(updfl, void, env, i32) /* dvinit */ diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 06c4485e55..dc2a65f3f9 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -6747,6 +6747,15 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_UPDFL: gen_helper_updfl(cpu_env, cpu_gpr_d[r1]); break; + case OPC2_32_RR_UTOF: + gen_helper_utof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + break; + case OPC2_32_RR_FTOIZ: + gen_helper_ftoiz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + break; + case OPC2_32_RR_QSEED_F: + gen_helper_qseed(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } @@ -7019,9 +7028,9 @@ static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx) } break; case OPC2_32_RRPW_INSERT: - if (pos + width <= 31) { + if (pos + width <= 32) { tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], - width, pos); + pos, width); } break; default: @@ -8804,6 +8813,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) ctx.singlestep_enabled = cs->singlestep_enabled; ctx.bstate = BS_NONE; ctx.mem_idx = cpu_mmu_index(env, false); + ctx.hflags = (uint32_t)tb->flags; tcg_clear_temp_count(); gen_tb_start(tb); |