diff options
| author | Stefan Markovic <smarkovic@wavecomp.com> | 2018-08-20 12:00:27 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-08-24 17:51:59 +0200 |
| commit | 0bbc0396809f6caaaf96863dafe738e94f9b73ea (patch) | |
| tree | b4da29e5768a51cbd850b14865f294447dd683e0 | |
| parent | b3979b6fc3faf286968a239d09c7adf36d0fade6 (diff) | |
| download | qemu-0bbc0396809f6caaaf96863dafe738e94f9b73ea.zip | |
target/mips: Prevent switching mode related to Config3 ISA bit for nanoMIPS
Only if Config3.ISA is 3 (microMIPS), the mode should be switched in
cpu_state_reset(). Config3.ISA is 1 for nanoMIPS processors, and no mode
change should happen.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
| -rw-r--r-- | target/mips/translate.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 4f95b9a6e8..7fb322b47d 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -21841,8 +21841,8 @@ void cpu_state_reset(CPUMIPSState *env) env->CP0_Status |= (1 << CP0St_FR); } - if (env->CP0_Config3 & (1 << CP0C3_ISA)) { - /* microMIPS on reset when Config3.ISA == {1, 3} */ + if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { + /* microMIPS on reset when Config3.ISA is 3 */ env->hflags |= MIPS_HFLAG_M16; } |