bin/yosys
bin/yosys-config
bin/yosys-filterlib
bin/yosys-smtbmc
bin/yosys-witness
%%DATADIR%%/abc9_map.v
%%DATADIR%%/abc9_model.v
%%DATADIR%%/abc9_unmap.v
%%DATADIR%%/achronix/speedster22i/cells_map.v
%%DATADIR%%/achronix/speedster22i/cells_sim.v
%%DATADIR%%/adff2dff.v
%%DATADIR%%/anlogic/arith_map.v
%%DATADIR%%/anlogic/brams.txt
%%DATADIR%%/anlogic/brams_map.v
%%DATADIR%%/anlogic/cells_map.v
%%DATADIR%%/anlogic/cells_sim.v
%%DATADIR%%/anlogic/eagle_bb.v
%%DATADIR%%/anlogic/lutrams.txt
%%DATADIR%%/anlogic/lutrams_map.v
%%DATADIR%%/cells.lib
%%DATADIR%%/cmp2lcu.v
%%DATADIR%%/cmp2lut.v
%%DATADIR%%/cmp2softlogic.v
%%DATADIR%%/coolrunner2/cells_counter_map.v
%%DATADIR%%/coolrunner2/cells_latch.v
%%DATADIR%%/coolrunner2/cells_sim.v
%%DATADIR%%/coolrunner2/tff_extract.v
%%DATADIR%%/coolrunner2/xc2_dff.lib
%%DATADIR%%/dff2ff.v
%%DATADIR%%/ecp5/arith_map.v
%%DATADIR%%/ecp5/brams.txt
%%DATADIR%%/ecp5/brams_map.v
%%DATADIR%%/ecp5/cells_bb.v
%%DATADIR%%/ecp5/cells_ff.vh
%%DATADIR%%/ecp5/cells_io.vh
%%DATADIR%%/ecp5/cells_map.v
%%DATADIR%%/ecp5/cells_sim.v
%%DATADIR%%/ecp5/dsp_map.v
%%DATADIR%%/ecp5/latches_map.v
%%DATADIR%%/ecp5/lutrams.txt
%%DATADIR%%/ecp5/lutrams_map.v
%%DATADIR%%/efinix/arith_map.v
%%DATADIR%%/efinix/brams.txt
%%DATADIR%%/efinix/brams_map.v
%%DATADIR%%/efinix/cells_map.v
%%DATADIR%%/efinix/cells_sim.v
%%DATADIR%%/efinix/gbuf_map.v
%%DATADIR%%/fabulous/arith_map.v
%%DATADIR%%/fabulous/cells_map.v
%%DATADIR%%/fabulous/ff_map.v
%%DATADIR%%/fabulous/io_map.v
%%DATADIR%%/fabulous/latches_map.v
%%DATADIR%%/fabulous/prims.v
%%DATADIR%%/fabulous/ram_regfile.txt
%%DATADIR%%/fabulous/regfile_map.v
%%DATADIR%%/gate2lut.v
%%DATADIR%%/gatemate/arith_map.v
%%DATADIR%%/gatemate/brams.txt
%%DATADIR%%/gatemate/brams_init_20.vh
%%DATADIR%%/gatemate/brams_init_40.vh
%%DATADIR%%/gatemate/brams_map.v
%%DATADIR%%/gatemate/cells_bb.v
%%DATADIR%%/gatemate/cells_sim.v
%%DATADIR%%/gatemate/inv_map.v
%%DATADIR%%/gatemate/lut_map.v
%%DATADIR%%/gatemate/lut_tree_cells.genlib
%%DATADIR%%/gatemate/lut_tree_map.v
%%DATADIR%%/gatemate/mul_map.v
%%DATADIR%%/gatemate/mux_map.v
%%DATADIR%%/gatemate/reg_map.v
%%DATADIR%%/gowin/arith_map.v
%%DATADIR%%/gowin/brams.txt
%%DATADIR%%/gowin/brams_map.v
%%DATADIR%%/gowin/cells_map.v
%%DATADIR%%/gowin/cells_sim.v
%%DATADIR%%/gowin/cells_xtra.v
%%DATADIR%%/gowin/lutrams.txt
%%DATADIR%%/gowin/lutrams_map.v
%%DATADIR%%/greenpak4/cells_blackbox.v
%%DATADIR%%/greenpak4/cells_latch.v
%%DATADIR%%/greenpak4/cells_map.v
%%DATADIR%%/greenpak4/cells_sim.v
%%DATADIR%%/greenpak4/cells_sim_ams.v
%%DATADIR%%/greenpak4/cells_sim_digital.v
%%DATADIR%%/greenpak4/cells_sim_wip.v
%%DATADIR%%/greenpak4/gp_dff.lib
%%DATADIR%%/ice40/abc9_model.v
%%DATADIR%%/ice40/arith_map.v
%%DATADIR%%/ice40/brams.txt
%%DATADIR%%/ice40/brams_map.v
%%DATADIR%%/ice40/cells_map.v
%%DATADIR%%/ice40/cells_sim.v
%%DATADIR%%/ice40/dsp_map.v
%%DATADIR%%/ice40/ff_map.v
%%DATADIR%%/ice40/latches_map.v
%%DATADIR%%/ice40/spram.txt
%%DATADIR%%/ice40/spram_map.v
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
%%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
%%DATADIR%%/include/backends/rtlil/rtlil_backend.h
%%DATADIR%%/include/frontends/ast/ast.h
%%DATADIR%%/include/frontends/ast/ast_binding.h
%%DATADIR%%/include/frontends/blif/blifparse.h
%%DATADIR%%/include/kernel/binding.h
%%DATADIR%%/include/kernel/cellaigs.h
%%DATADIR%%/include/kernel/celledges.h
%%DATADIR%%/include/kernel/celltypes.h
%%DATADIR%%/include/kernel/consteval.h
%%DATADIR%%/include/kernel/constids.inc
%%DATADIR%%/include/kernel/cost.h
%%DATADIR%%/include/kernel/ff.h
%%DATADIR%%/include/kernel/ffinit.h
%%DATADIR%%/include/kernel/ffmerge.h
%%DATADIR%%/include/kernel/fmt.h
%%DATADIR%%/include/kernel/fstdata.h
%%DATADIR%%/include/kernel/hashlib.h
%%DATADIR%%/include/kernel/json.h
%%DATADIR%%/include/kernel/log.h
%%DATADIR%%/include/kernel/macc.h
%%DATADIR%%/include/kernel/mem.h
%%DATADIR%%/include/kernel/modtools.h
%%DATADIR%%/include/kernel/qcsat.h
%%DATADIR%%/include/kernel/register.h
%%DATADIR%%/include/kernel/rtlil.h
%%DATADIR%%/include/kernel/satgen.h
%%DATADIR%%/include/kernel/sigtools.h
%%DATADIR%%/include/kernel/timinginfo.h
%%DATADIR%%/include/kernel/utils.h
%%DATADIR%%/include/kernel/yosys.h
%%DATADIR%%/include/kernel/yw.h
%%DATADIR%%/include/libs/ezsat/ezminisat.h
%%DATADIR%%/include/libs/ezsat/ezsat.h
%%DATADIR%%/include/libs/fst/fstapi.h
%%DATADIR%%/include/libs/json11/json11.hpp
%%DATADIR%%/include/libs/sha1/sha1.h
%%DATADIR%%/include/passes/fsm/fsmdata.h
%%DATADIR%%/intel/common/altpll_bb.v
%%DATADIR%%/intel/common/brams_m9k.txt
%%DATADIR%%/intel/common/brams_map_m9k.v
%%DATADIR%%/intel/common/ff_map.v
%%DATADIR%%/intel/common/m9k_bb.v
%%DATADIR%%/intel/cyclone10lp/cells_map.v
%%DATADIR%%/intel/cyclone10lp/cells_sim.v
%%DATADIR%%/intel/cycloneiv/cells_map.v
%%DATADIR%%/intel/cycloneiv/cells_sim.v
%%DATADIR%%/intel/cycloneive/cells_map.v
%%DATADIR%%/intel/cycloneive/cells_sim.v
%%DATADIR%%/intel/max10/cells_map.v
%%DATADIR%%/intel/max10/cells_sim.v
%%DATADIR%%/intel_alm/common/abc9_map.v
%%DATADIR%%/intel_alm/common/abc9_model.v
%%DATADIR%%/intel_alm/common/abc9_unmap.v
%%DATADIR%%/intel_alm/common/alm_map.v
%%DATADIR%%/intel_alm/common/alm_sim.v
%%DATADIR%%/intel_alm/common/arith_alm_map.v
%%DATADIR%%/intel_alm/common/bram_m10k.txt
%%DATADIR%%/intel_alm/common/bram_m10k_map.v
%%DATADIR%%/intel_alm/common/bram_m20k.txt
%%DATADIR%%/intel_alm/common/bram_m20k_map.v
%%DATADIR%%/intel_alm/common/dff_map.v
%%DATADIR%%/intel_alm/common/dff_sim.v
%%DATADIR%%/intel_alm/common/dsp_map.v
%%DATADIR%%/intel_alm/common/dsp_sim.v
%%DATADIR%%/intel_alm/common/lutram_mlab.txt
%%DATADIR%%/intel_alm/common/megafunction_bb.v
%%DATADIR%%/intel_alm/common/mem_sim.v
%%DATADIR%%/intel_alm/common/misc_sim.v
%%DATADIR%%/intel_alm/common/quartus_rename.v
%%DATADIR%%/intel_alm/cyclonev/cells_sim.v
%%DATADIR%%/lattice/arith_map_ccu2c.v
%%DATADIR%%/lattice/arith_map_ccu2d.v
%%DATADIR%%/lattice/brams_16kd.txt
%%DATADIR%%/lattice/brams_8kc.txt
%%DATADIR%%/lattice/brams_map_16kd.v
%%DATADIR%%/lattice/brams_map_8kc.v
%%DATADIR%%/lattice/ccu2c_sim.vh
%%DATADIR%%/lattice/ccu2d_sim.vh
%%DATADIR%%/lattice/cells_bb_ecp5.v
%%DATADIR%%/lattice/cells_bb_xo2.v
%%DATADIR%%/lattice/cells_bb_xo3.v
%%DATADIR%%/lattice/cells_bb_xo3d.v
%%DATADIR%%/lattice/cells_ff.vh
%%DATADIR%%/lattice/cells_io.vh
%%DATADIR%%/lattice/cells_map.v
%%DATADIR%%/lattice/cells_sim_ecp5.v
%%DATADIR%%/lattice/cells_sim_xo2.v
%%DATADIR%%/lattice/cells_sim_xo3.v
%%DATADIR%%/lattice/cells_sim_xo3d.v
%%DATADIR%%/lattice/common_sim.vh
%%DATADIR%%/lattice/dsp_map_18x18.v
%%DATADIR%%/lattice/latches_map.v
%%DATADIR%%/lattice/lutrams.txt
%%DATADIR%%/lattice/lutrams_map.v
%%DATADIR%%/mul2dsp.v
%%DATADIR%%/nexus/arith_map.v
%%DATADIR%%/nexus/brams.txt
%%DATADIR%%/nexus/brams_map.v
%%DATADIR%%/nexus/cells_map.v
%%DATADIR%%/nexus/cells_sim.v
%%DATADIR%%/nexus/cells_xtra.v
%%DATADIR%%/nexus/dsp_map.v
%%DATADIR%%/nexus/latches_map.v
%%DATADIR%%/nexus/lrams.txt
%%DATADIR%%/nexus/lrams_map.v
%%DATADIR%%/nexus/lutrams.txt
%%DATADIR%%/nexus/lutrams_map.v
%%DATADIR%%/nexus/parse_init.vh
%%DATADIR%%/pmux2mux.v
%%DATADIR%%/python3/smtio.py
%%DATADIR%%/python3/ywio.py
%%DATADIR%%/quicklogic/common/cells_sim.v
%%DATADIR%%/quicklogic/pp3/abc9_map.v
%%DATADIR%%/quicklogic/pp3/abc9_model.v
%%DATADIR%%/quicklogic/pp3/abc9_unmap.v
%%DATADIR%%/quicklogic/pp3/cells_map.v
%%DATADIR%%/quicklogic/pp3/cells_sim.v
%%DATADIR%%/quicklogic/pp3/ffs_map.v
%%DATADIR%%/quicklogic/pp3/latches_map.v
%%DATADIR%%/quicklogic/pp3/lut_map.v
%%DATADIR%%/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
%%DATADIR%%/quicklogic/qlf_k6n10f/arith_map.v
%%DATADIR%%/quicklogic/qlf_k6n10f/bram_types_sim.v
%%DATADIR%%/quicklogic/qlf_k6n10f/brams_map.v
%%DATADIR%%/quicklogic/qlf_k6n10f/brams_sim.v
%%DATADIR%%/quicklogic/qlf_k6n10f/cells_sim.v
%%DATADIR%%/quicklogic/qlf_k6n10f/dsp_final_map.v
%%DATADIR%%/quicklogic/qlf_k6n10f/dsp_map.v
%%DATADIR%%/quicklogic/qlf_k6n10f/dsp_sim.v
%%DATADIR%%/quicklogic/qlf_k6n10f/ffs_map.v
%%DATADIR%%/quicklogic/qlf_k6n10f/libmap_brams.txt
%%DATADIR%%/quicklogic/qlf_k6n10f/libmap_brams_map.v
%%DATADIR%%/quicklogic/qlf_k6n10f/sram1024x18_mem.v
%%DATADIR%%/quicklogic/qlf_k6n10f/ufifo_ctl.v
%%DATADIR%%/sf2/arith_map.v
%%DATADIR%%/sf2/cells_map.v
%%DATADIR%%/sf2/cells_sim.v
%%DATADIR%%/simcells.v
%%DATADIR%%/simlib.v
%%DATADIR%%/smtmap.v
%%DATADIR%%/techmap.v
%%DATADIR%%/xilinx/abc9_model.v
%%DATADIR%%/xilinx/arith_map.v
%%DATADIR%%/xilinx/brams_defs.vh
%%DATADIR%%/xilinx/brams_xc2v.txt
%%DATADIR%%/xilinx/brams_xc2v_map.v
%%DATADIR%%/xilinx/brams_xc3sda.txt
%%DATADIR%%/xilinx/brams_xc3sda_map.v
%%DATADIR%%/xilinx/brams_xc4v.txt
%%DATADIR%%/xilinx/brams_xc4v_map.v
%%DATADIR%%/xilinx/brams_xc5v_map.v
%%DATADIR%%/xilinx/brams_xc6v_map.v
%%DATADIR%%/xilinx/brams_xcu_map.v
%%DATADIR%%/xilinx/brams_xcv.txt
%%DATADIR%%/xilinx/brams_xcv_map.v
%%DATADIR%%/xilinx/cells_map.v
%%DATADIR%%/xilinx/cells_sim.v
%%DATADIR%%/xilinx/cells_xtra.v
%%DATADIR%%/xilinx/ff_map.v
%%DATADIR%%/xilinx/lut_map.v
%%DATADIR%%/xilinx/lutrams_xc5v.txt
%%DATADIR%%/xilinx/lutrams_xc5v_map.v
%%DATADIR%%/xilinx/lutrams_xcu.txt
%%DATADIR%%/xilinx/lutrams_xcv.txt
%%DATADIR%%/xilinx/lutrams_xcv_map.v
%%DATADIR%%/xilinx/mux_map.v
%%DATADIR%%/xilinx/urams.txt
%%DATADIR%%/xilinx/urams_map.v
%%DATADIR%%/xilinx/xc3s_mult_map.v
%%DATADIR%%/xilinx/xc3sda_dsp_map.v
%%DATADIR%%/xilinx/xc4v_dsp_map.v
%%DATADIR%%/xilinx/xc5v_dsp_map.v
%%DATADIR%%/xilinx/xc6s_dsp_map.v
%%DATADIR%%/xilinx/xc7_dsp_map.v
%%DATADIR%%/xilinx/xcu_dsp_map.v