Age | Commit message (Collapse) | Author |
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Changelog at <http://www.geuz.org/gmsh/doc/VERSIONS>.
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PR: 93682
Submitted by: Pedro F. Giffuni <giffunip@asme.org>
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Submitted by: tdb
Approved by: portmgr (linimon)
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Discussed with: kris
Approved by: portmgr (implicit)
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Approved by: portmgr (implicit)
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Approved by: portmgr (marcus, previously)
Spotted by: kris
Pointy hat to: me
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Approved by: portmgr (marcus)
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Submitted by: pointyhat
Approved by: portmgr (implicit)
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Approved by: portmgr (kris)
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PR: 93518
Submitted by: maintainer
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Submitted by: Pedro F. Giffuni <giffunip@asme.org>
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PR: 92782
Submitted by: Pedro F. Giffuni <giffunip@asme.org>
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amd64.
Since I'm there, pet portlint.
Tested by: Pedro F. Giffuni <giffunip (at) yahoo.com>
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o cleanup
PR: 92782
Submitted by: Pedro F.Giffuni <giffunip@asme.org>
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PR: 92799
Submitted by: TAOKA Fumiyoshi <fmysh (at) iijmio-mail.jp>
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partitioning, static mapping, and sparse matrix block ordering.
Its purpose of Scotch is to apply graph theory, with a divide and conquer
approach, to scientific computing problems such as graph and mesh partitioning,
static mapping, and sparse matrix ordering, in application domains ranging from
structural mechanics to operating systems or bio-chemistry.
Note: there is an older tarball included in Aster's distfile, but I prefer
a separate distfile from the official site.
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- Use foo-[0-9]* for CONFLICTS
Submitted by: "Thomas E. Zander" <riggs@rrr.de> (maintainer)
PR: ports/92575
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- Update WWW and master site
- use USE_TCL and USE_TK
Submitted by: Ports fury
PR: ports/92611
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Changelog at <http://www.geuz.org/gmsh/doc/VERSIONS>.
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causing confusion in FreshPorts.
Submitted by: Pedro F. Giffuni <giffunip (at) yahoo.com>
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Approved by: krion@
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Approved by: krion@
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Approved by: krion@
PR: ports/88711 (related)
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Approved by: krion@
PR: ports/88711 (related)
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Changelog at <http://iut-tice.ujf-grenoble.fr/cao/news.txt>.
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Changelog at <http://iut-tice.ujf-grenoble.fr/cao/news.txt>.
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Tested by: Pedro F. Giffuni <giffunip (at) yahoo.com>
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Changelog at <http://iut-tice.ujf-grenoble.fr/cao/news.txt>.
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Changelog at <http://www.geuz.org/gmsh/doc/VERSIONS>.
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Changelog at <http://iut-tice.ujf-grenoble.fr/cao/news.txt>.
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- Shared lib version and PORTREVISION bumb for all affected ports.
While I'm here:
- Remove USE_MESA knob where it was (35 ports).
It marked as depricated for 2 years.
PR: ports/90247
Submitted by: Ermal Lu?i <eri--@albabsd.org>
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Changelog at <http://iut-tice.ujf-grenoble.fr/cao/news.txt>.
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PR: 91252
Submitted by: Pedro F. Giffuni <giffunip@asme.org>
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Changelog at <http://iut-tice.ujf-grenoble.fr/cao/news.txt>.
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When I ported this I added amd64 to give the "benefit of
doubt" however I had the chance top test it but it doesn't
work, it coredumps.
PR: ports/91188
Submitted by: Pedro F. Giffuni <giffunip@asme.org>
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PR: ports/91094
Submitted by: Jean Milanez Melo <jmelo@freebsdbrasil.com.br> (maintainer)
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Another version upgrade. The amd64 problem has been fixed,
both as a patch here and in the HEAD of the sf.net repository.
This has only been tested on 6.0/ia32 and 6.0/amd64, my 7
box is down and I don't have 4 or 5 anymore. :/
PR: ports/91037
Submitted by: Erik Greenwald <erik@smluc.org>
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GPL Cver is a full 1995 P1364 Verilog standard HDL simulator.
It also implements some of the 2001 P1364 standard features
including all three PLI interfaces (tf_, acc_ and vpi_) as
defined in the 2001 Language Reference Manual (LRM).
Verilog is the name for both a language for describing
electronic hardware called a hardware description language
(HDL) and the name of the program that simulates HDL circuit
descriptions to verify that described circuits will function
correctly when the are constructed. Verilog is used only
for describing digital logic circuits. Other HDLs such as
Spice are used for describing analog circuits. There is an
IEEE standard named P1364 that standardizes the Verilog HDL
and the behavior of Verilog simulators. Verilog is officially
defined in the IEEE P1364 Language Reference Manual (LRM)
that can be purchased from IEEE. There are many good books
for learning that teach the Verilog HDL and/or that teach
digital circuit design using Verilog.
WWW: http://www.pragmatic-c.com/gpl-cver/
PR: ports/80968
Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
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Changelog at <http://iut-tice.ujf-grenoble.fr/cao/news.txt>.
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- Update to 27
- Use a static pkg-plist
- Pass maintainership to submitter
PR: ports/90818
Submitted by: Soeren Straarup <xride@x12.dk>
Submitted by: pointyhat (kris)
Pointy hat to: garga
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