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| author | bors[bot] <26634292+bors[bot]@users.noreply.github.com> | 2022-10-19 07:29:12 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-10-19 07:29:12 +0000 |
| commit | d9c773f47598666c322a5e25c1f3d2681c3d3c01 (patch) | |
| tree | 01c3a1a35dc8624f661c1bf9843f3df0de82536a /examples/stm32l5/Cargo.toml | |
| parent | a669f4cfd8b178e924482cf008d5eaec7889e415 (diff) | |
| parent | 6c5d81ada52bfac1592c7be025038a3eea3acc42 (diff) | |
| download | embassy-d9c773f47598666c322a5e25c1f3d2681c3d3c01.zip | |
Merge #1014
1014: Add memory barriers to H7 flash driver to mitigate PGSERR errors r=lulf a=matoushybl
The stm32h7xx-hal uses only the ordering barrier, while the CubeMX uses the DSB and ISB instructions, to be on the safe side, both are used here.
Without the barrier, the PG bit is not set, when the writes are being done, resulting in an error.
Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
Diffstat (limited to 'examples/stm32l5/Cargo.toml')
0 files changed, 0 insertions, 0 deletions