diff --git a/libavutil/riscv/Makefile b/libavutil/riscv/Makefile
index 1597154..6294b5d 100644
--- a/libavutil/riscv/Makefile
+++ b/libavutil/riscv/Makefile
@@ -2,4 +2,5 @@ OBJS +=     riscv/float_dsp_init.o \
             riscv/fixed_dsp_init.o \
             riscv/cpu.o
 RVV-OBJS += riscv/float_dsp_rvv.o \
-            riscv/fixed_dsp_rvv.o
+            riscv/fixed_dsp_rvv.o \
+            riscv/cpu_rvv.o
diff --git a/libavutil/riscv/cpu.c b/libavutil/riscv/cpu.c
index fa45c0a..76485fd 100644
--- a/libavutil/riscv/cpu.c
+++ b/libavutil/riscv/cpu.c
@@ -28,6 +28,8 @@
 #define HWCAP_RV(letter) (1ul << ((letter) - 'A'))
 #endif
 
+int ff_has_compliant_rvv(void);
+
 int ff_get_cpu_flags_riscv(void)
 {
     int ret = 0;
@@ -44,7 +46,7 @@ int ff_get_cpu_flags_riscv(void)
         ret |= AV_CPU_FLAG_RVB_ADDR | AV_CPU_FLAG_RVB_BASIC;
 
     /* The V extension implies all Zve* functional subsets */
-    if (hwcap & HWCAP_RV('V'))
+    if ((hwcap & HWCAP_RV('V')) && ff_has_compliant_rvv())
         ret |= AV_CPU_FLAG_RVV_I32 | AV_CPU_FLAG_RVV_I64
              | AV_CPU_FLAG_RVV_F32 | AV_CPU_FLAG_RVV_F64;
 #endif
diff --git a/libavutil/riscv/cpu_rvv.S b/libavutil/riscv/cpu_rvv.S
new file mode 100644
index 0000000..0b25e00
--- /dev/null
+++ b/libavutil/riscv/cpu_rvv.S
@@ -0,0 +1,47 @@
+/******************************************************************************
+ * Copyright © 2018, VideoLAN and dav1d authors
+ * Copyright © 2024, Nathan Egge
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ *    list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+
+#include "asm.S"
+
+#define L(x) .L ## x
+
+// This function detects non-compliant RVV 0.7.1 hardware which reports support
+//  for the V extension through HWCAP, by intentionally setting tail and mask
+//  agnostic vector configurations that were only introduced in RVV 0.9 spec.
+// Existing non-compliant (pre RVV 1.0) hardware will set the VILL bit in VTYPE
+//  (indicating an illegal vector configuration) which is stored in the XLEN-1
+//  bit position, thus a simple sign check is sufficient for detection.
+// The same code will work on RV32 if there is ever non-compliant rv32gcv.
+func ff_has_compliant_rvv, ext=v
+  vsetvli zero, zero, e8, m1, ta, ma
+  csrr a1, vtype
+  li a0, 0
+  blt a1, x0, L(rvv071)
+  li a0, 1
+L(rvv071):
+  ret
+endfunc