blob: a061e473bef0a2ec505c05cb02d2fae94897be54 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
|
" Author: Masahiro H https://github.com/mshr-h
" Description: iverilog for verilog files
function! ale_linters#verilog#iverilog#Handle(buffer, lines) abort
" Look for lines like the following.
"
" tb_me_top.v:37: warning: Instantiating module me_top with dangling input port 1 (rst_n) floating.
" tb_me_top.v:17: syntax error
" memory_single_port.v:2: syntax error
" tb_me_top.v:17: error: Invalid module instantiation
let l:pattern = '^[^:]\+:\(\d\+\): \(warning\|error\|syntax error\)\(: \(.\+\)\)\?'
let l:output = []
for l:line in a:lines
let l:match = matchlist(l:line, l:pattern)
if len(l:match) == 0
continue
endif
let l:line = l:match[1] + 0
let l:type = l:match[2] =~# 'error' ? 'E' : 'W'
let l:text = l:match[2] ==# 'syntax error' ? 'syntax error' : l:match[4]
call add(l:output, {
\ 'bufnr': a:buffer,
\ 'lnum': l:line,
\ 'text': l:text,
\ 'type': l:type,
\})
endfor
return l:output
endfunction
call ale#linter#Define('verilog', {
\ 'name': 'iverilog',
\ 'output_stream': 'stderr',
\ 'executable': 'iverilog',
\ 'command': 'iverilog -t null -Wall %t',
\ 'callback': 'ale_linters#verilog#iverilog#Handle',
\})
|