From b8bf7b220d0f7ab461ed830b125f9dbc42a7836a Mon Sep 17 00:00:00 2001 From: John Gentile Date: Sun, 27 Jan 2019 04:46:33 -0500 Subject: Add VHDL Support & Newer Verilog Linters (#2229) * Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters --- test/handler/test_ghdl_handler.vader | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100644 test/handler/test_ghdl_handler.vader (limited to 'test/handler/test_ghdl_handler.vader') diff --git a/test/handler/test_ghdl_handler.vader b/test/handler/test_ghdl_handler.vader new file mode 100644 index 00000000..a0f5edac --- /dev/null +++ b/test/handler/test_ghdl_handler.vader @@ -0,0 +1,26 @@ +Before: + runtime ale_linters/vhdl/ghdl.vim + +After: + call ale#linter#Reset() + +Execute(The ghdl handler should parse lines correctly): + AssertEqual + \ [ + \ { + \ 'lnum': 41, + \ 'col' : 5, + \ 'type': 'E', + \ 'text': "error: 'begin' is expected instead of 'if'" + \ }, + \ { + \ 'lnum': 12, + \ 'col' : 8, + \ 'type': 'E', + \ 'text': ' no declaration for "i0"' + \ }, + \ ], + \ ale_linters#vhdl#ghdl#Handle(bufnr(''), [ + \ "dff_en.vhd:41:5:error: 'begin' is expected instead of 'if'", + \ '/path/to/file.vhdl:12:8: no declaration for "i0"', + \ ]) -- cgit v1.2.3