From c8f669249ae064aa014ec180df3934f0a82cab29 Mon Sep 17 00:00:00 2001
From: Nathan Sharp <39231199+nwsharp@users.noreply.github.com>
Date: Mon, 12 Jul 2021 06:39:53 -0600
Subject: Add Yosys linter for Verilog files. (#3713)

* Add yosys for verilog files.

* Add handler test for yosys.

* fix typo in yosys handler test

* fix array order in yosys handler test

* add yosys linter to filetype defaults test

* fix duplicate tag

* add 'yosys' to 'ale-supported-languages-and-tools.txt'
---
 doc/ale.txt | 1 +
 1 file changed, 1 insertion(+)

(limited to 'doc/ale.txt')

diff --git a/doc/ale.txt b/doc/ale.txt
index 53dd2ea2..f2800ff0 100644
--- a/doc/ale.txt
+++ b/doc/ale.txt
@@ -3067,6 +3067,7 @@ documented in additional help files.
     verilator.............................|ale-verilog-verilator|
     vlog..................................|ale-verilog-vlog|
     xvlog.................................|ale-verilog-xvlog|
+    yosys.................................|ale-verilog-yosys|
   vhdl....................................|ale-vhdl-options|
     ghdl..................................|ale-vhdl-ghdl|
     hdl-checker...........................|ale-vhdl-hdl-checker|
-- 
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