| Age | Commit message (Expand) | Author |
|---|---|---|
| 2021-07-12 | Add Yosys linter for Verilog files. (#3713) | Nathan Sharp |
| 2020-08-06 | Adds hdl_checker LSP support (#2804) | Andre Souto |
| 2019-01-27 | Add VHDL Support & Newer Verilog Linters (#2229) | John Gentile |
| 2017-07-08 | Use equal signs for language documentation sections | w0rp |
| 2017-06-29 | Adds an option to pass additional arguments to the verilog/verilator … (#698) | Tarik Graba |
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index : ale | |
| Check syntax in Vim asynchronously and fix files, with Language Server Protocol (LSP) support | cos |
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