1 files changed, 48 insertions, 0 deletions
diff --git a/test/handler/test_verilator_handler.vader b/test/handler/test_verilator_handler.vader
new file mode 100644
index 00000000..5e51b5c9
--- /dev/null
+++ b/test/handler/test_verilator_handler.vader
@@ -0,0 +1,48 @@
+Before:
+  runtime ale_linters/verilog/verilator.vim
+
+After:
+  call ale#linter#Reset()
+
+
+Execute (The verilator handler should parse legacy messages with only line numbers):
+  AssertEqual
+  \ [
+  \   {
+  \     'lnum': 3,
+  \     'type': 'E',
+  \     'text': 'syntax error, unexpected IDENTIFIER'
+  \   },
+  \   {
+  \     'lnum': 10,
+  \     'type': 'W',
+  \     'text': 'Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).'
+  \   },
+  \ ],
+  \ ale_linters#verilog#verilator#Handle(bufnr(''), [
+  \ '%Error: foo_verilator_linted.v:3: syntax error, unexpected IDENTIFIER',
+  \ '%Warning-BLKSEQ: bar_verilator_linted.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).',
+  \ ])
+
+
+Execute (The verilator handler should parse new format messages with line and column numbers):
+  AssertEqual
+  \ [
+  \   {
+  \     'lnum': 3,
+  \     'col' : 1,
+  \     'type': 'E',
+  \     'text': 'syntax error, unexpected endmodule, expecting ;'
+  \   },
+  \   {
+  \     'lnum': 4,
+  \     'col' : 6,
+  \     'type': 'W',
+  \     'text': 'Signal is not used: r'
+  \   },
+  \ ],
+  \ ale_linters#verilog#verilator#Handle(bufnr(''), [
+  \ '%Error: bar_verilator_linted.v:3:1: syntax error, unexpected endmodule, expecting ;',
+  \ '%Warning-UNUSED: foo_verilator_linted.v:4:6: Signal is not used: r',
+  \ ])
+