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-rw-r--r--test/handler/test_verilator_handler.vader3
1 files changed, 0 insertions, 3 deletions
diff --git a/test/handler/test_verilator_handler.vader b/test/handler/test_verilator_handler.vader
index 59ec1361..efcf6619 100644
--- a/test/handler/test_verilator_handler.vader
+++ b/test/handler/test_verilator_handler.vader
@@ -4,7 +4,6 @@ Before:
After:
call ale#linter#Reset()
-
Execute (The verilator handler should parse legacy messages with only line numbers):
AssertEqual
\ [
@@ -26,7 +25,6 @@ Execute (The verilator handler should parse legacy messages with only line numbe
\ '%Warning-BLKSEQ: bar.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=).',
\ ])
-
Execute (The verilator handler should parse new format messages with line and column numbers):
AssertEqual
\ [
@@ -49,4 +47,3 @@ Execute (The verilator handler should parse new format messages with line and co
\ '%Error: bar.v:3:1: syntax error, unexpected endmodule, expecting ;',
\ '%Warning-UNUSED: foo.v:4:6: Signal is not used: r',
\ ])
-