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authorJohn Gentile <johncgentile17@gmail.com>2019-01-27 04:46:33 -0500
committerw0rp <w0rp@users.noreply.github.com>2019-01-27 09:46:33 +0000
commitb8bf7b220d0f7ab461ed830b125f9dbc42a7836a (patch)
tree0f4b112c5c082b156ca8393d3242cb3fe762bfd8 /test/handler
parent91c1fc3bb396dfcb495c484db7d39193df8826eb (diff)
downloadale-b8bf7b220d0f7ab461ed830b125f9dbc42a7836a.zip
Add VHDL Support & Newer Verilog Linters (#2229)
* Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
Diffstat (limited to 'test/handler')
-rw-r--r--test/handler/test_ghdl_handler.vader26
-rw-r--r--test/handler/test_vcom_handler.vader36
-rw-r--r--test/handler/test_vlog_handler.vader24
-rw-r--r--test/handler/test_xvhdl_handler.vader24
-rw-r--r--test/handler/test_xvlog_handler.vader18
5 files changed, 128 insertions, 0 deletions
diff --git a/test/handler/test_ghdl_handler.vader b/test/handler/test_ghdl_handler.vader
new file mode 100644
index 00000000..a0f5edac
--- /dev/null
+++ b/test/handler/test_ghdl_handler.vader
@@ -0,0 +1,26 @@
+Before:
+ runtime ale_linters/vhdl/ghdl.vim
+
+After:
+ call ale#linter#Reset()
+
+Execute(The ghdl handler should parse lines correctly):
+ AssertEqual
+ \ [
+ \ {
+ \ 'lnum': 41,
+ \ 'col' : 5,
+ \ 'type': 'E',
+ \ 'text': "error: 'begin' is expected instead of 'if'"
+ \ },
+ \ {
+ \ 'lnum': 12,
+ \ 'col' : 8,
+ \ 'type': 'E',
+ \ 'text': ' no declaration for "i0"'
+ \ },
+ \ ],
+ \ ale_linters#vhdl#ghdl#Handle(bufnr(''), [
+ \ "dff_en.vhd:41:5:error: 'begin' is expected instead of 'if'",
+ \ '/path/to/file.vhdl:12:8: no declaration for "i0"',
+ \ ])
diff --git a/test/handler/test_vcom_handler.vader b/test/handler/test_vcom_handler.vader
new file mode 100644
index 00000000..943b525a
--- /dev/null
+++ b/test/handler/test_vcom_handler.vader
@@ -0,0 +1,36 @@
+Before:
+ runtime ale_linters/vhdl/vcom.vim
+
+After:
+ call ale#linter#Reset()
+
+Execute(The vcom handler should parse lines correctly):
+ AssertEqual
+ \ [
+ \ {
+ \ 'lnum': 218,
+ \ 'type': 'W',
+ \ 'text': '(vcom-1236) Shared variables must be of a protected type.'
+ \ },
+ \ {
+ \ 'lnum': 73,
+ \ 'type': 'E',
+ \ 'text': '(vcom-1136) Unknown identifier "aresetn".'
+ \ },
+ \ {
+ \ 'lnum': 73,
+ \ 'type': 'E',
+ \ 'text': 'Bad resolution function (STD_LOGIC) for type (error).'
+ \ },
+ \ {
+ \ 'lnum': 73,
+ \ 'type': 'E',
+ \ 'text': 'near ":": (vcom-1576) expecting ";" or ")".'
+ \ },
+ \ ],
+ \ ale_linters#vhdl#vcom#Handle(bufnr(''), [
+ \ '** Warning: ../path/to/file.vhd(218): (vcom-1236) Shared variables must be of a protected type.',
+ \ '** Error: tb_file.vhd(73): (vcom-1136) Unknown identifier "aresetn".',
+ \ '** Error: tb_file.vhd(73): Bad resolution function (STD_LOGIC) for type (error).',
+ \ '** Error: tb_file.vhd(73): near ":": (vcom-1576) expecting ";" or ")".',
+ \ ])
diff --git a/test/handler/test_vlog_handler.vader b/test/handler/test_vlog_handler.vader
new file mode 100644
index 00000000..a70665db
--- /dev/null
+++ b/test/handler/test_vlog_handler.vader
@@ -0,0 +1,24 @@
+Before:
+ runtime ale_linters/verilog/vlog.vim
+
+After:
+ call ale#linter#Reset()
+
+Execute(The vlog handler should parse lines correctly):
+ AssertEqual
+ \ [
+ \ {
+ \ 'lnum': 7,
+ \ 'type': 'W',
+ \ 'text': '(vlog-2623) Undefined variable: C.'
+ \ },
+ \ {
+ \ 'lnum': 1,
+ \ 'type': 'E',
+ \ 'text': '(vlog-13294) Identifier must be declared with a port mode: C.'
+ \ },
+ \ ],
+ \ ale_linters#verilog#vlog#Handle(bufnr(''), [
+ \ '** Warning: add.v(7): (vlog-2623) Undefined variable: C.',
+ \ '** Error: file.v(1): (vlog-13294) Identifier must be declared with a port mode: C.',
+ \ ])
diff --git a/test/handler/test_xvhdl_handler.vader b/test/handler/test_xvhdl_handler.vader
new file mode 100644
index 00000000..b90539b8
--- /dev/null
+++ b/test/handler/test_xvhdl_handler.vader
@@ -0,0 +1,24 @@
+Before:
+ runtime ale_linters/vhdl/xvhdl.vim
+
+After:
+ call ale#linter#Reset()
+
+Execute(The xvhdl handler should parse lines correctly):
+ AssertEqual
+ \ [
+ \ {
+ \ 'lnum': 17,
+ \ 'type': 'E',
+ \ 'text': '[VRFC 10-91] aresetn is not declared '
+ \ },
+ \ {
+ \ 'lnum': 128,
+ \ 'type': 'E',
+ \ 'text': '[VRFC 10-91] m_axis_tx_tdata is not declared '
+ \ },
+ \ ],
+ \ ale_linters#vhdl#xvhdl#Handle(bufnr(''), [
+ \ 'ERROR: [VRFC 10-91] aresetn is not declared [/path/to/file.vhd:17]',
+ \ 'ERROR: [VRFC 10-91] m_axis_tx_tdata is not declared [/home/user/tx_data.vhd:128]',
+ \ ])
diff --git a/test/handler/test_xvlog_handler.vader b/test/handler/test_xvlog_handler.vader
new file mode 100644
index 00000000..2e1f83fc
--- /dev/null
+++ b/test/handler/test_xvlog_handler.vader
@@ -0,0 +1,18 @@
+Before:
+ runtime ale_linters/verilog/xvlog.vim
+
+After:
+ call ale#linter#Reset()
+
+Execute(The xvlog handler should parse lines correctly):
+ AssertEqual
+ \ [
+ \ {
+ \ 'lnum': 5,
+ \ 'type': 'E',
+ \ 'text': '[VRFC 10-1412] syntax error near output '
+ \ },
+ \ ],
+ \ ale_linters#verilog#xvlog#Handle(bufnr(''), [
+ \ 'ERROR: [VRFC 10-1412] syntax error near output [/path/to/file.v:5]',
+ \ ])