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authorJohn Gentile <johncgentile17@gmail.com>2019-01-27 04:46:33 -0500
committerw0rp <w0rp@users.noreply.github.com>2019-01-27 09:46:33 +0000
commitb8bf7b220d0f7ab461ed830b125f9dbc42a7836a (patch)
tree0f4b112c5c082b156ca8393d3242cb3fe762bfd8 /test/handler/test_xvhdl_handler.vader
parent91c1fc3bb396dfcb495c484db7d39193df8826eb (diff)
downloadale-b8bf7b220d0f7ab461ed830b125f9dbc42a7836a.zip
Add VHDL Support & Newer Verilog Linters (#2229)
* Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
Diffstat (limited to 'test/handler/test_xvhdl_handler.vader')
-rw-r--r--test/handler/test_xvhdl_handler.vader24
1 files changed, 24 insertions, 0 deletions
diff --git a/test/handler/test_xvhdl_handler.vader b/test/handler/test_xvhdl_handler.vader
new file mode 100644
index 00000000..b90539b8
--- /dev/null
+++ b/test/handler/test_xvhdl_handler.vader
@@ -0,0 +1,24 @@
+Before:
+ runtime ale_linters/vhdl/xvhdl.vim
+
+After:
+ call ale#linter#Reset()
+
+Execute(The xvhdl handler should parse lines correctly):
+ AssertEqual
+ \ [
+ \ {
+ \ 'lnum': 17,
+ \ 'type': 'E',
+ \ 'text': '[VRFC 10-91] aresetn is not declared '
+ \ },
+ \ {
+ \ 'lnum': 128,
+ \ 'type': 'E',
+ \ 'text': '[VRFC 10-91] m_axis_tx_tdata is not declared '
+ \ },
+ \ ],
+ \ ale_linters#vhdl#xvhdl#Handle(bufnr(''), [
+ \ 'ERROR: [VRFC 10-91] aresetn is not declared [/path/to/file.vhd:17]',
+ \ 'ERROR: [VRFC 10-91] m_axis_tx_tdata is not declared [/home/user/tx_data.vhd:128]',
+ \ ])