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authorAndre Souto <suoto@users.noreply.github.com>2020-08-06 13:20:54 +0100
committerGitHub <noreply@github.com>2020-08-06 13:20:54 +0100
commit5b3da60cea542aa16c0bf9ea084242df834b2a7a (patch)
treeafdc70356691024f71d940d8a2310a4abd547820 /doc/ale-verilog.txt
parent711c90c523bedcd644386e253d0840e0a9fc684e (diff)
downloadale-5b3da60cea542aa16c0bf9ea084242df834b2a7a.zip
Adds hdl_checker LSP support (#2804)
* Added hdl_checker support * Added hdl_checker tests HDL Checker searches for files when no config file is found, which could lead to very long searches when the user is not really on a project setting
Diffstat (limited to 'doc/ale-verilog.txt')
-rw-r--r--doc/ale-verilog.txt18
1 files changed, 17 insertions, 1 deletions
diff --git a/doc/ale-verilog.txt b/doc/ale-verilog.txt
index 94b820b8..01af63c2 100644
--- a/doc/ale-verilog.txt
+++ b/doc/ale-verilog.txt
@@ -3,7 +3,10 @@ ALE Verilog/SystemVerilog Integration *ale-verilog-options*
===============================================================================
-ALE can use four different linters for Verilog HDL:
+ALE can use five different linters for Verilog HDL:
+
+ HDL Checker
+ Using `hdl_checker --lsp`
iverilog:
Using `iverilog -t null -Wall`
@@ -26,6 +29,9 @@ defining 'g:ale_linters' variable:
\ let g:ale_linters = {'systemverilog' : ['verilator'],}
<
+===============================================================================
+General notes
+
Linters/compilers that utilize a "work" directory for analyzing designs- such
as ModelSim and Vivado- can be passed the location of these directories as
part of their respective option strings listed below. This is useful for
@@ -40,6 +46,16 @@ changing. This can happen in the form of hangs or crashes. To help prevent
this when using these linters, it may help to run linting less frequently; for
example, only when a file is saved.
+HDL Checker is an alternative for some of the issues described above. It wraps
+around ghdl, Vivado and ModelSim/Questa and, when using the latter, it can
+handle mixed language (VHDL, Verilog, SystemVerilog) designs.
+
+===============================================================================
+hdl-checker *ale-verilog-hdl-checker*
+
+See |ale-vhdl-hdl-checker|
+
+
===============================================================================
iverilog *ale-verilog-iverilog*