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| author | Nathan Sharp <39231199+nwsharp@users.noreply.github.com> | 2021-07-12 06:39:53 -0600 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-07-12 21:39:53 +0900 |
| commit | c8f669249ae064aa014ec180df3934f0a82cab29 (patch) | |
| tree | 3ba9d4e7e7d25cfddde068b4b868a5cde2da8ce5 /doc/ale-supported-languages-and-tools.txt | |
| parent | 9a9fd24b17db32e452609e68e6a9729461625720 (diff) | |
| download | ale-c8f669249ae064aa014ec180df3934f0a82cab29.zip | |
Add Yosys linter for Verilog files. (#3713)
* Add yosys for verilog files.
* Add handler test for yosys.
* fix typo in yosys handler test
* fix array order in yosys handler test
* add yosys linter to filetype defaults test
* fix duplicate tag
* add 'yosys' to 'ale-supported-languages-and-tools.txt'
Diffstat (limited to 'doc/ale-supported-languages-and-tools.txt')
| -rw-r--r-- | doc/ale-supported-languages-and-tools.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/doc/ale-supported-languages-and-tools.txt b/doc/ale-supported-languages-and-tools.txt index 639e1833..283caf06 100644 --- a/doc/ale-supported-languages-and-tools.txt +++ b/doc/ale-supported-languages-and-tools.txt @@ -550,6 +550,7 @@ Notes: * `verilator` * `vlog` * `xvlog` + * `yosys` * VHDL * `ghdl` * `vcom` |