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authorJohn Gentile <johncgentile17@gmail.com>2019-01-27 04:46:33 -0500
committerw0rp <w0rp@users.noreply.github.com>2019-01-27 09:46:33 +0000
commitb8bf7b220d0f7ab461ed830b125f9dbc42a7836a (patch)
tree0f4b112c5c082b156ca8393d3242cb3fe762bfd8 /doc/ale-scss.txt
parent91c1fc3bb396dfcb495c484db7d39193df8826eb (diff)
downloadale-b8bf7b220d0f7ab461ed830b125f9dbc42a7836a.zip
Add VHDL Support & Newer Verilog Linters (#2229)
* Added VHDL file support with ghdl compiler * Update ghdl.vim * Create vcom.vim * Create xvhdl.vim * Update xvlog.vim * Added documentation for VHDL & Verilog linters * Added tests to VHDL & Verilog linters
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