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| author | Bjorn Neergaard <bjorn@neersighted.com> | 2016-10-10 18:43:45 -0500 |
|---|---|---|
| committer | Bjorn Neergaard <bjorn@neersighted.com> | 2016-10-11 06:14:26 -0500 |
| commit | fb4b797dd22b2ec225542c97e5c0c4195edf037e (patch) | |
| tree | be6bc337e1403aaded57cfaaf0ce506e73cfb225 /ale_linters/verilog | |
| parent | ca4badfb3a0ae73d4fcac3512c8cfae2a6a94f03 (diff) | |
| download | ale-fb4b797dd22b2ec225542c97e5c0c4195edf037e.zip | |
Use explicit scope in all ale_linters
vint -s is now clean
Diffstat (limited to 'ale_linters/verilog')
| -rw-r--r-- | ale_linters/verilog/iverilog.vim | 24 | ||||
| -rw-r--r-- | ale_linters/verilog/verilator.vim | 24 |
2 files changed, 24 insertions, 24 deletions
diff --git a/ale_linters/verilog/iverilog.vim b/ale_linters/verilog/iverilog.vim index 02df6f84..373c6731 100644 --- a/ale_linters/verilog/iverilog.vim +++ b/ale_linters/verilog/iverilog.vim @@ -14,32 +14,32 @@ function! ale_linters#verilog#iverilog#Handle(buffer, lines) " tb_me_top.v:17: syntax error " memory_single_port.v:2: syntax error " tb_me_top.v:17: error: Invalid module instantiation - let pattern = '^[^:]\+:\(\d\+\): \(warning\|error\|syntax error\)\(: \(.\+\)\)\?' - let output = [] + let l:pattern = '^[^:]\+:\(\d\+\): \(warning\|error\|syntax error\)\(: \(.\+\)\)\?' + let l:output = [] - for line in a:lines - let l:match = matchlist(line, pattern) + for l:line in a:lines + let l:match = matchlist(l:line, l:pattern) if len(l:match) == 0 continue endif - let line = l:match[1] + 0 - let type = l:match[2] ==# 'warning' ? 'W' : 'E' - let text = l:match[2] ==# 'syntax error' ? 'syntax error' : l:match[4] + let l:line = l:match[1] + 0 + let l:type = l:match[2] ==# 'warning' ? 'W' : 'E' + let l:text = l:match[2] ==# 'syntax error' ? 'syntax error' : l:match[4] - call add(output, { + call add(l:output, { \ 'bufnr': a:buffer, - \ 'lnum': line, + \ 'lnum': l:line, \ 'vcol': 0, \ 'col': 1, - \ 'text': text, - \ 'type': type, + \ 'text': l:text, + \ 'type': l:type, \ 'nr': -1, \}) endfor - return output + return l:output endfunction call ale#linter#Define('verilog', { diff --git a/ale_linters/verilog/verilator.vim b/ale_linters/verilog/verilator.vim index 4878ad3e..4fd0a295 100644 --- a/ale_linters/verilog/verilator.vim +++ b/ale_linters/verilog/verilator.vim @@ -16,32 +16,32 @@ function! ale_linters#verilog#verilator#Handle(buffer, lines) " %Warning-UNDRIVEN: test.v:3: Signal is not driven: clk " %Warning-UNUSED: test.v:4: Signal is not used: dout " %Warning-BLKSEQ: test.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=). - let pattern = '^%\(Warning\|Error\)[^:]*:[^:]\+:\(\d\+\): \(.\+\)$' - let output = [] + let l:pattern = '^%\(Warning\|Error\)[^:]*:[^:]\+:\(\d\+\): \(.\+\)$' + let l:output = [] - for line in a:lines - let l:match = matchlist(line, pattern) + for l:line in a:lines + let l:match = matchlist(l:line, l:pattern) if len(l:match) == 0 continue endif - let line = l:match[2] + 0 - let type = l:match[1] ==# 'Error' ? 'E' : 'W' - let text = l:match[3] + let l:line = l:match[2] + 0 + let l:type = l:match[1] ==# 'Error' ? 'E' : 'W' + let l:text = l:match[3] - call add(output, { + call add(l:output, { \ 'bufnr': a:buffer, - \ 'lnum': line, + \ 'lnum': l:line, \ 'vcol': 0, \ 'col': 1, - \ 'text': text, - \ 'type': type, + \ 'text': l:text, + \ 'type': l:type, \ 'nr': -1, \}) endfor - return output + return l:output endfunction call ale#linter#Define('verilog', { |