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| author | Masahiro H <mshr-h@users.noreply.github.com> | 2017-01-15 21:39:13 +0900 |
|---|---|---|
| committer | w0rp <w0rp@users.noreply.github.com> | 2017-01-15 12:39:13 +0000 |
| commit | 74e7a283c052969afdb71a06199b11995626fdd9 (patch) | |
| tree | 21599a5d85e1d07fdbce81a1f30307756c8f58de /ale_linters/verilog/verilator.vim | |
| parent | f412b4f96fa49f4ed856db25c10bdf4b9c2e4cec (diff) | |
| download | ale-74e7a283c052969afdb71a06199b11995626fdd9.zip | |
Improve Verilator support (#205) (#258)
* improve-verilator-support
* fix for linter
Diffstat (limited to 'ale_linters/verilog/verilator.vim')
| -rw-r--r-- | ale_linters/verilog/verilator.vim | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/ale_linters/verilog/verilator.vim b/ale_linters/verilog/verilator.vim index 440edeca..d8e105a2 100644 --- a/ale_linters/verilog/verilator.vim +++ b/ale_linters/verilog/verilator.vim @@ -10,7 +10,7 @@ function! ale_linters#verilog#verilator#Handle(buffer, lines) " %Warning-UNDRIVEN: test.v:3: Signal is not driven: clk " %Warning-UNUSED: test.v:4: Signal is not used: dout " %Warning-BLKSEQ: test.v:10: Blocking assignments (=) in sequential (flop or latch) block; suggest delayed assignments (<=). - let l:pattern = '^%\(Warning\|Error\)[^:]*:[^:]\+:\(\d\+\): \(.\+\)$' + let l:pattern = '^%\(Warning\|Error\)[^:]*:\([^:]\+\):\(\d\+\): \(.\+\)$' let l:output = [] for l:line in a:lines @@ -20,19 +20,22 @@ function! ale_linters#verilog#verilator#Handle(buffer, lines) continue endif - let l:line = l:match[2] + 0 + let l:line = l:match[3] + 0 let l:type = l:match[1] ==# 'Error' ? 'E' : 'W' - let l:text = l:match[3] + let l:text = l:match[4] + let l:file = l:match[2] - call add(l:output, { - \ 'bufnr': a:buffer, - \ 'lnum': l:line, - \ 'vcol': 0, - \ 'col': 1, - \ 'text': l:text, - \ 'type': l:type, - \ 'nr': -1, - \}) + if(l:file =~# '_verilator_linted.v') + call add(l:output, { + \ 'bufnr': a:buffer, + \ 'lnum': l:line, + \ 'vcol': 0, + \ 'col': 1, + \ 'text': l:text, + \ 'type': l:type, + \ 'nr': -1, + \}) + endif endfor return l:output @@ -42,6 +45,6 @@ call ale#linter#Define('verilog', { \ 'name': 'verilator', \ 'output_stream': 'stderr', \ 'executable': 'verilator', -\ 'command': g:ale#util#stdin_wrapper . ' .v verilator --lint-only -Wall -Wno-DECLFILENAME', +\ 'command': g:ale#util#stdin_wrapper . ' _verilator_linted.v verilator --lint-only -Wall -Wno-DECLFILENAME', \ 'callback': 'ale_linters#verilog#verilator#Handle', \}) |