diff options
author | John Gentile <johncgentile17@gmail.com> | 2019-01-27 04:46:33 -0500 |
---|---|---|
committer | w0rp <w0rp@users.noreply.github.com> | 2019-01-27 09:46:33 +0000 |
commit | b8bf7b220d0f7ab461ed830b125f9dbc42a7836a (patch) | |
tree | 0f4b112c5c082b156ca8393d3242cb3fe762bfd8 /README.md | |
parent | 91c1fc3bb396dfcb495c484db7d39193df8826eb (diff) | |
download | ale-b8bf7b220d0f7ab461ed830b125f9dbc42a7836a.zip |
Add VHDL Support & Newer Verilog Linters (#2229)
* Added VHDL file support with ghdl compiler
* Update ghdl.vim
* Create vcom.vim
* Create xvhdl.vim
* Update xvlog.vim
* Added documentation for VHDL & Verilog linters
* Added tests to VHDL & Verilog linters
Diffstat (limited to 'README.md')
-rw-r--r-- | README.md | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -201,7 +201,8 @@ formatting. | Thrift | [thrift](http://thrift.apache.org/) | | TypeScript | [eslint](http://eslint.org/), [prettier](https://github.com/prettier/prettier), [tslint](https://github.com/palantir/tslint), [tsserver](https://github.com/Microsoft/TypeScript/wiki/Standalone-Server-%28tsserver%29), typecheck | | VALA | [uncrustify](https://github.com/uncrustify/uncrustify) | -| Verilog | [iverilog](https://github.com/steveicarus/iverilog), [verilator](http://www.veripool.org/projects/verilator/wiki/Intro) | +| Verilog | [iverilog](https://github.com/steveicarus/iverilog), [verilator](http://www.veripool.org/projects/verilator/wiki/Intro), [vlog](https://www.mentor.com/products/fv/questa/), [xvlog](https://www.xilinx.com/products/design-tools/vivado.html) | +| VHDL | [ghdl](https://github.com/ghdl/ghdl), [vcom](https://www.mentor.com/products/fv/questa/), [xvhdl](https://www.xilinx.com/products/design-tools/vivado.html) | | Vim | [vint](https://github.com/Kuniwak/vint) | | Vim help^ | [alex](https://github.com/wooorm/alex) !!, [proselint](http://proselint.com/), [write-good](https://github.com/btford/write-good) | | Vue | [prettier](https://github.com/prettier/prettier), [vls](https://github.com/vuejs/vetur/tree/master/server) | |