From 6c5d81ada52bfac1592c7be025038a3eea3acc42 Mon Sep 17 00:00:00 2001 From: Matous Hybl Date: Tue, 18 Oct 2022 22:42:02 +0200 Subject: Add memory barriers to H7 flash driver to mitigate PGSERR errors The stm32h7xx-hal uses only the ordering barrier, while the CubeMX uses the DSB and ISB instructions, to be on the safe side, both are used here. --- embassy-stm32/src/flash/h7.rs | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/embassy-stm32/src/flash/h7.rs b/embassy-stm32/src/flash/h7.rs index 7ce0ac77..3f2129de 100644 --- a/embassy-stm32/src/flash/h7.rs +++ b/embassy-stm32/src/flash/h7.rs @@ -39,6 +39,10 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error w.set_psize(2); // 32 bits at once }); + cortex_m::asm::isb(); + cortex_m::asm::dsb(); + atomic_polyfill::fence(atomic_polyfill::Ordering::SeqCst); + let ret = { let mut ret: Result<(), Error> = Ok(()); let mut offset = offset; @@ -64,6 +68,10 @@ pub(crate) unsafe fn blocking_write(offset: u32, buf: &[u8]) -> Result<(), Error bank.cr().write(|w| w.set_pg(false)); + cortex_m::asm::isb(); + cortex_m::asm::dsb(); + atomic_polyfill::fence(atomic_polyfill::Ordering::SeqCst); + ret } -- cgit v1.2.3